Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	248616	1		T1	4		T2	778		T3	2
auto[FlashEraseBank]	267810	1		T2	727		T4	862		T6	512

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	262170	1		T1	2		T4	1667		T6	1086
auto[FlashOpProgram]	233448	1		T1	2		T2	1505		T3	1
auto[FlashOpErase]	16808	1		T3	1		T23	37		T24	48
auto[FlashOpInvalid]	4000	1		T89	200		T205	200		T155	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	262170	1		T1	2		T4	1667		T6	1086
op[FlashOpProgram]	233448	1		T1	2		T2	1505		T3	1
op[FlashOpErase]	16808	1		T3	1		T23	37		T24	48
read_erase_read	573	1		T23	5		T24	5		T25	4
read_prog_read	908	1		T1	1		T7	2		T18	9

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	370431	1		T1	4		T2	1322		T3	2
auto[FlashPartInfo]	142398	1		T2	173		T6	215		T7	193
auto[FlashPartInfo1]	957	1		T6	2		T17	35		T18	1
auto[FlashPartInfo2]	2640	1		T2	10		T6	7		T7	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189186	1		T1	2		T4	1667		T6	862
auto[FlashPartData]	auto[FlashOpProgram]	173715	1		T1	2		T2	1322		T3	1
auto[FlashPartData]	auto[FlashOpErase]	3616	1		T3	1		T23	37		T24	33
auto[FlashPartData]	auto[FlashOpInvalid]	3914	1		T89	198		T205	200		T155	196
auto[FlashPartInfo]	auto[FlashOpRead]	70493	1		T6	215		T7	96		T17	175
auto[FlashPartInfo]	auto[FlashOpProgram]	58667	1		T2	173		T7	97		T18	37
auto[FlashPartInfo]	auto[FlashOpErase]	13166	1		T24	15		T89	1		T115	323
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T89	2		T155	4		T389	6
auto[FlashPartInfo1]	auto[FlashOpRead]	787	1		T6	2		T17	35		T18	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T25	1		T79	32		T80	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T144	1		T390	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T144	2		T390	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1704	1		T6	7		T7	7		T17	44
auto[FlashPartInfo2]	auto[FlashOpProgram]	902	1		T2	10		T18	1		T56	12
auto[FlashPartInfo2]	auto[FlashOpErase]	24	1		T30	1		T389	1		T77	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T389	2		T391	2		T390	4