Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33215	1		T23	24		T24	20		T89	400
auto[1]	31	1		T315	1		T104	4		T316	1
auto[2]	50	1		T317	1		T59	4		T60	8
auto[3]	237	1		T28	1		T30	11		T151	18

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8384	1		T23	6		T24	5		T89	100
evic_idx[1]	8390	1		T23	6		T24	5		T89	100
evic_idx[2]	8388	1		T23	6		T24	5		T89	100
evic_idx[3]	8371	1		T23	6		T24	5		T89	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32712	1		T89	400		T115	628		T116	732
evic_op[2]	329	1		T24	4		T28	1		T315	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8116	1		T89	100		T115	157		T116	183
evic_idx[0]	evic_op[1]	auto[1]	7	1		T318	1		T319	4		T320	2
evic_idx[0]	evic_op[1]	auto[2]	4	1		T319	4		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	56	1		T30	4		T151	5		T152	3
evic_idx[0]	evic_op[2]	auto[0]	71	1		T24	1		T257	10		T258	10
evic_idx[0]	evic_op[2]	auto[1]	1	1		T104	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T321	1		T322	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	4	1		T202	1		T323	1		T324	1
evic_idx[1]	evic_op[1]	auto[0]	8118	1		T89	100		T115	157		T116	183
evic_idx[1]	evic_op[1]	auto[1]	9	1		T318	2		T325	3		T319	3
evic_idx[1]	evic_op[1]	auto[2]	4	1		T319	4		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	54	1		T30	2		T151	5		T152	2
evic_idx[1]	evic_op[2]	auto[0]	69	1		T24	1		T257	10		T258	10
evic_idx[1]	evic_op[2]	auto[1]	1	1		T104	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T326	1		T321	2		-	-
evic_idx[1]	evic_op[2]	auto[3]	9	1		T327	1		T328	1		T329	1
evic_idx[2]	evic_op[1]	auto[0]	8115	1		T89	100		T115	157		T116	183
evic_idx[2]	evic_op[1]	auto[1]	3	1		T319	2		T320	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	7	1		T330	1		T319	3		T331	3
evic_idx[2]	evic_op[1]	auto[3]	50	1		T30	2		T151	4		T152	4
evic_idx[2]	evic_op[2]	auto[0]	71	1		T24	1		T332	1		T257	10
evic_idx[2]	evic_op[2]	auto[1]	3	1		T315	1		T104	1		T333	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T317	1		T321	1		T322	1
evic_idx[2]	evic_op[2]	auto[3]	13	1		T40	1		T334	1		T335	1
evic_idx[3]	evic_op[1]	auto[0]	8112	1		T89	100		T115	157		T116	183
evic_idx[3]	evic_op[1]	auto[1]	4	1		T319	2		T320	2		-	-
evic_idx[3]	evic_op[1]	auto[2]	7	1		T330	1		T319	3		T331	3
evic_idx[3]	evic_op[1]	auto[3]	46	1		T30	3		T151	4		T152	2
evic_idx[3]	evic_op[2]	auto[0]	71	1		T24	1		T257	10		T258	10
evic_idx[3]	evic_op[2]	auto[1]	3	1		T104	1		T316	1		T333	1
evic_idx[3]	evic_op[2]	auto[3]	5	1		T28	1		T336	1		T337	1