Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	8668	1		T259	2633		T304	1578		T305	1919
rd_lvl[2]	19999	1		T4	12622		T259	1966		T304	775
rd_lvl[3]	15063	1		T4	354		T17	873		T259	956
rd_lvl[4]	43928	1		T4	1		T17	234		T259	900
rd_lvl[5]	18036	1		T17	5		T259	790		T306	1740
rd_lvl[6]	18972	1		T38	382		T259	6		T262	519
rd_lvl[7]	13063	1		T38	297		T259	758		T76	80
rd_lvl[8]	12873	1		T38	74		T259	757		T76	26
rd_lvl[9]	7769	1		T4	1		T38	153		T259	980
rd_lvl[10]	11789	1		T38	153		T259	532		T262	40
rd_lvl[11]	5178	1		T4	1		T259	20		T75	622
rd_lvl[12]	6624	1		T259	1		T75	1086		T307	1326
rd_lvl[13]	1044	1		T308	383		T309	12		T37	167
rd_lvl[14]	6738	1		T259	19		T310	1525		T35	2
rd_lvl[15]	2874	1		T310	274		T36	454		T311	421