Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	298585	1		T1	2		T2	1506		T3	2
all_pins[1]	298585	1		T1	2		T2	1506		T3	2
all_pins[2]	298585	1		T1	2		T2	1506		T3	2
all_pins[3]	298585	1		T1	2		T2	1506		T3	2
all_pins[4]	298585	1		T1	2		T2	1506		T3	2
all_pins[5]	298585	1		T1	2		T2	1506		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1470104	1		T1	12		T2	7531		T3	12
values[0x1]	321406	1		T2	1505		T4	14647		T17	1376
transitions[0x0=>0x1]	287726	1		T2	1505		T4	13332		T17	1328
transitions[0x1=>0x0]	287704	1		T2	1505		T4	13332		T17	1328

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	298426	1		T1	2		T2	1506		T3	2
all_pins[0]	values[0x1]	159	1		T244	6		T245	2		T246	5
all_pins[0]	transitions[0x0=>0x1]	80	1		T244	1		T245	2		T246	4
all_pins[0]	transitions[0x1=>0x0]	71	1		T244	2		T245	1		T298	2
all_pins[1]	values[0x0]	298435	1		T1	2		T2	1506		T3	2
all_pins[1]	values[0x1]	150	1		T244	7		T245	1		T246	1
all_pins[1]	transitions[0x0=>0x1]	119	1		T244	5		T245	1		T246	1
all_pins[1]	transitions[0x1=>0x0]	3881	1		T36	1294		T311	1128		T338	172
all_pins[2]	values[0x0]	294673	1		T1	2		T2	1506		T3	2
all_pins[2]	values[0x1]	3912	1		T36	1294		T311	1128		T338	172
all_pins[2]	transitions[0x0=>0x1]	54	1		T244	1		T246	1		T298	1
all_pins[2]	transitions[0x1=>0x0]	192945	1		T4	12979		T17	1112		T38	1059
all_pins[3]	values[0x0]	101782	1		T1	2		T2	1506		T3	2
all_pins[3]	values[0x1]	196803	1		T4	12979		T17	1112		T38	1059
all_pins[3]	transitions[0x0=>0x1]	167139	1		T4	11664		T17	1064		T38	906
all_pins[3]	transitions[0x1=>0x0]	90650	1		T2	1505		T4	353		T17	216
all_pins[4]	values[0x0]	178271	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	120314	1		T2	1505		T4	1668		T17	264
all_pins[4]	transitions[0x0=>0x1]	120302	1		T2	1505		T4	1668		T17	264
all_pins[4]	transitions[0x1=>0x0]	56	1		T244	2		T246	2		T298	1
all_pins[5]	values[0x0]	298517	1		T1	2		T2	1506		T3	2
all_pins[5]	values[0x1]	68	1		T244	2		T246	2		T298	1
all_pins[5]	transitions[0x0=>0x1]	32	1		T244	1		T298	1		T299	2
all_pins[5]	transitions[0x1=>0x0]	101	1		T244	4		T245	1		T246	2