Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	308629	1		T1	2		T2	2		T3	2
all_values[1]	308629	1		T1	2		T2	2		T3	2
all_values[2]	308629	1		T1	2		T2	2		T3	2
all_values[3]	308629	1		T1	2		T2	2		T3	2
all_values[4]	308629	1		T1	2		T2	2		T3	2
all_values[5]	308629	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	623707	1		T1	12		T2	12		T3	12
auto[1]	1228067	1		T16	19568		T29	688		T34	161236

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	910093	1		T1	7		T2	7		T3	7
auto[1]	941681	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	308494	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	135	1		T268	4		T269	2		T270	2
all_values[1]	auto[0]	auto[1]	308463	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	166	1		T268	3		T269	4		T270	3
all_values[2]	auto[0]	auto[0]	1614	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	53	1		T268	3		T269	3		T325	1
all_values[2]	auto[1]	auto[0]	306896	1		T16	4892		T29	172		T34	40309
all_values[2]	auto[1]	auto[1]	66	1		T269	1		T270	1		T327	1
all_values[3]	auto[0]	auto[0]	1667	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	52	1		T268	1		T270	1		T325	1
all_values[3]	auto[1]	auto[0]	87110	1		T16	1630		T29	86		T157	1588
all_values[3]	auto[1]	auto[1]	219800	1		T16	3262		T29	86		T34	40309
all_values[4]	auto[0]	auto[0]	1141	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	531	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	203183	1		T16	3261		T29	86		T34	38656
all_values[4]	auto[1]	auto[1]	103774	1		T16	1631		T29	86		T34	1653
all_values[5]	auto[0]	auto[0]	1604	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	88	1		T23	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	306878	1		T16	4892		T29	172		T34	40309
all_values[5]	auto[1]	auto[1]	59	1		T268	2		T270	1		T325	3