Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00
Crosses 16 0 16 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
erase_cp 2 0 2 100.00 100 1 1 0
op_cp 4 0 4 100.00 100 1 1 0
op_evict_cp 5 0 5 100.00 100 1 1 0
part_cp 4 0 4 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
op_part_cross 16 0 16 100.00 100 1 1 0


Summary for Variable erase_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for erase_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashErasePage] 233423 1 T1 4 T2 441 T3 1
auto[FlashEraseBank] 265723 1 T1 6 T2 512 T4 454



Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashOpRead] 250509 1 T1 5 T2 953 T3 1
auto[FlashOpProgram] 230310 1 T1 5 T17 1 T18 1194
auto[FlashOpErase] 14327 1 T5 9 T41 140 T30 12
auto[FlashOpInvalid] 4000 1 T213 200 T214 200 T154 200



Summary for Variable op_evict_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for op_evict_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
op[FlashOpRead] 250509 1 T1 5 T2 953 T3 1
op[FlashOpProgram] 230310 1 T1 5 T17 1 T18 1194
op[FlashOpErase] 14327 1 T5 9 T41 140 T30 12
read_erase_read 546 1 T5 2 T30 3 T65 5
read_prog_read 814 1 T1 4 T17 1 T20 1



Summary for Variable part_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for part_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] 364755 1 T1 10 T2 630 T4 871
auto[FlashPartInfo] 130982 1 T2 311 T3 1 T4 223
auto[FlashPartInfo1] 872 1 T2 2 T4 2 T21 3
auto[FlashPartInfo2] 2537 1 T2 10 T4 9 T17 1



Summary for Cross op_part_cross

Samples crossed: part_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for op_part_cross

Bins
part_cpop_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] auto[FlashOpRead] 183150 1 T1 5 T2 630 T4 871
auto[FlashPartData] auto[FlashOpProgram] 174016 1 T1 5 T17 1 T18 929
auto[FlashPartData] auto[FlashOpErase] 3665 1 T65 30 T66 29 T67 8
auto[FlashPartData] auto[FlashOpInvalid] 3924 1 T213 198 T214 196 T154 192
auto[FlashPartInfo] auto[FlashOpRead] 65106 1 T2 311 T3 1 T4 223
auto[FlashPartInfo] auto[FlashOpProgram] 55188 1 T18 257 T5 256 T25 1
auto[FlashPartInfo] auto[FlashOpErase] 10634 1 T5 9 T41 140 T30 12
auto[FlashPartInfo] auto[FlashOpInvalid] 54 1 T214 4 T154 4 T406 4
auto[FlashPartInfo1] auto[FlashOpRead] 684 1 T2 2 T4 2 T21 3
auto[FlashPartInfo1] auto[FlashOpProgram] 169 1 T66 1 T59 32 T152 32
auto[FlashPartInfo1] auto[FlashOpErase] 9 1 T65 1 T154 1 T407 1
auto[FlashPartInfo1] auto[FlashOpInvalid] 10 1 T154 2 T407 2 T131 4
auto[FlashPartInfo2] auto[FlashOpRead] 1569 1 T2 10 T4 9 T17 1
auto[FlashPartInfo2] auto[FlashOpProgram] 937 1 T18 8 T56 5 T21 1
auto[FlashPartInfo2] auto[FlashOpErase] 19 1 T66 1 T146 2 T213 1
auto[FlashPartInfo2] auto[FlashOpInvalid] 12 1 T213 2 T154 2 T406 2

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