Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28314	1		T1	20		T41	312		T30	4
auto[1]	30	1		T206	1		T38	1		T255	4
auto[2]	73	1		T146	1		T255	3		T285	5
auto[3]	211	1		T124	4		T193	1		T35	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7160	1		T1	5		T41	78		T30	1
evic_idx[1]	7157	1		T1	5		T41	78		T30	1
evic_idx[2]	7166	1		T1	5		T41	78		T30	1
evic_idx[3]	7145	1		T1	5		T41	78		T30	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27694	1		T41	312		T30	4		T88	528
evic_op[2]	303	1		T1	20		T124	4		T193	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6863	1		T41	78		T30	1		T88	132
evic_idx[0]	evic_op[1]	auto[1]	5	1		T255	1		T408	1		T409	3
evic_idx[0]	evic_op[1]	auto[2]	12	1		T255	1		T285	1		T410	2
evic_idx[0]	evic_op[1]	auto[3]	43	1		T147	1		T146	4		T255	3
evic_idx[0]	evic_op[2]	auto[0]	61	1		T1	5		T411	1		T283	9
evic_idx[0]	evic_op[2]	auto[1]	3	1		T38	1		T412	1		T413	1
evic_idx[0]	evic_op[2]	auto[2]	3	1		T414	1		T415	1		T416	1
evic_idx[0]	evic_op[2]	auto[3]	12	1		T124	1		T193	1		T292	1
evic_idx[1]	evic_op[1]	auto[0]	6862	1		T41	78		T30	1		T88	132
evic_idx[1]	evic_op[1]	auto[1]	4	1		T255	1		T410	1		T408	1
evic_idx[1]	evic_op[1]	auto[2]	10	1		T285	2		T410	2		T417	3
evic_idx[1]	evic_op[1]	auto[3]	48	1		T147	2		T146	5		T255	2
evic_idx[1]	evic_op[2]	auto[0]	63	1		T1	5		T115	1		T116	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T203	1		T418	1		T419	1
evic_idx[1]	evic_op[2]	auto[2]	5	1		T292	1		T415	2		T420	1
evic_idx[1]	evic_op[2]	auto[3]	4	1		T124	1		T421	1		T422	1
evic_idx[2]	evic_op[1]	auto[0]	6864	1		T41	78		T30	1		T88	132
evic_idx[2]	evic_op[1]	auto[1]	7	1		T255	1		T408	3		T409	3
evic_idx[2]	evic_op[1]	auto[2]	7	1		T146	1		T285	1		T410	2
evic_idx[2]	evic_op[1]	auto[3]	52	1		T147	4		T146	3		T255	1
evic_idx[2]	evic_op[2]	auto[0]	64	1		T1	5		T113	1		T115	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T423	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	4	1		T203	1		T414	1		T424	1
evic_idx[2]	evic_op[2]	auto[3]	9	1		T124	1		T35	1		T425	1
evic_idx[3]	evic_op[1]	auto[0]	6862	1		T41	78		T30	1		T88	132
evic_idx[3]	evic_op[1]	auto[1]	5	1		T255	1		T408	1		T409	3
evic_idx[3]	evic_op[1]	auto[2]	13	1		T255	2		T285	1		T410	2
evic_idx[3]	evic_op[1]	auto[3]	37	1		T147	1		T146	2		T255	2
evic_idx[3]	evic_op[2]	auto[0]	60	1		T1	5		T283	9		T426	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T206	1		T427	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T428	1		T429	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	6	1		T124	1		T119	1		T136	1