Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	30732	1		T34	15515		T329	15217		-	-
rd_lvl[2]	25460	1		T34	10933		T329	10927		T330	1286
rd_lvl[3]	3983	1		T293	906		T331	1380		T330	551
rd_lvl[4]	25291	1		T293	743		T332	1180		T331	5953
rd_lvl[5]	19417	1		T293	82		T324	2165		T286	902
rd_lvl[6]	19561	1		T16	2678		T293	205		T324	1307
rd_lvl[7]	9354	1		T16	583		T282	1921		T286	932
rd_lvl[8]	12836	1		T32	835		T282	1621		T333	2874
rd_lvl[9]	1538	1		T32	231		T334	203		T333	298
rd_lvl[10]	2851	1		T16	1		T293	4		T334	603
rd_lvl[11]	1763	1		T32	30		T335	295		T336	144
rd_lvl[12]	13589	1		T157	1362		T337	1268		T338	298
rd_lvl[13]	5275	1		T157	226		T337	386		T293	205
rd_lvl[14]	5834	1		T29	73		T335	51		T339	194
rd_lvl[15]	3630	1		T29	12		T33	164		T338	155