Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	308629	1		T1	2		T2	2		T3	2
all_pins[1]	308629	1		T1	2		T2	2		T3	2
all_pins[2]	308629	1		T1	2		T2	2		T3	2
all_pins[3]	308629	1		T1	2		T2	2		T3	2
all_pins[4]	308629	1		T1	2		T2	2		T3	2
all_pins[5]	308629	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1553135	1		T1	12		T2	12		T3	12
values[0x1]	298639	1		T16	4893		T29	174		T34	28987
transitions[0x0=>0x1]	271827	1		T16	4892		T29	172		T34	26448
transitions[0x1=>0x0]	271815	1		T16	4892		T29	172		T34	26448

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	308494	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	135	1		T268	4		T269	2		T270	2
all_pins[0]	transitions[0x0=>0x1]	62	1		T268	3		T269	2		T325	1
all_pins[0]	transitions[0x1=>0x0]	93	1		T268	2		T269	4		T270	1
all_pins[1]	values[0x0]	308463	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	166	1		T268	3		T269	4		T270	3
all_pins[1]	transitions[0x0=>0x1]	129	1		T268	3		T269	3		T270	3
all_pins[1]	transitions[0x1=>0x0]	2803	1		T29	1		T33	88		T344	1035
all_pins[2]	values[0x0]	305789	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	2840	1		T29	1		T33	88		T344	1035
all_pins[2]	transitions[0x0=>0x1]	46	1		T269	1		T345	1		T346	2
all_pins[2]	transitions[0x1=>0x0]	181459	1		T16	3262		T29	85		T34	26448
all_pins[3]	values[0x0]	124376	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	184253	1		T16	3262		T29	86		T34	26448
all_pins[3]	transitions[0x0=>0x1]	160407	1		T16	3261		T29	85		T34	23909
all_pins[3]	transitions[0x1=>0x0]	87340	1		T16	1630		T29	86		T157	1588
all_pins[4]	values[0x0]	197443	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	111186	1		T16	1631		T29	87		T34	2539
all_pins[4]	transitions[0x0=>0x1]	111157	1		T16	1631		T29	87		T34	2539
all_pins[4]	transitions[0x1=>0x0]	30	1		T270	1		T325	1		T328	1
all_pins[5]	values[0x0]	308570	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	59	1		T268	2		T270	1		T325	3
all_pins[5]	transitions[0x0=>0x1]	26	1		T270	1		T325	2		T327	1
all_pins[5]	transitions[0x1=>0x0]	90	1		T268	1		T269	2		T270	1