Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	379377	1		T1	1		T2	2		T17	1
all_values[1]	379377	1		T1	1		T2	2		T17	1
all_values[2]	379377	1		T1	1		T2	2		T17	1
all_values[3]	379377	1		T1	1		T2	2		T17	1
all_values[4]	379377	1		T1	1		T2	2		T17	1
all_values[5]	379377	1		T1	1		T2	2		T17	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	765180	1		T1	6		T2	12		T17	6
auto[1]	1511082	1		T7	25192		T19	5752		T24	6124

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1118449	1		T1	4		T2	7		T17	4
auto[1]	1157813	1		T1	2		T2	5		T17	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	379229	1		T1	1		T2	2		T17	1
all_values[0]	auto[1]	auto[1]	148	1		T269	5		T270	1		T271	2
all_values[1]	auto[0]	auto[1]	379212	1		T1	1		T2	2		T17	1
all_values[1]	auto[1]	auto[1]	165	1		T269	6		T270	4		T329	5
all_values[2]	auto[0]	auto[0]	1626	1		T1	1		T2	2		T17	1
all_values[2]	auto[0]	auto[1]	62	1		T269	1		T271	1		T329	3
all_values[2]	auto[1]	auto[0]	377632	1		T7	6298		T19	1438		T24	1531
all_values[2]	auto[1]	auto[1]	57	1		T269	1		T270	1		T329	1
all_values[3]	auto[0]	auto[0]	1609	1		T1	1		T2	2		T17	1
all_values[3]	auto[0]	auto[1]	53	1		T269	2		T329	1		T330	2
all_values[3]	auto[1]	auto[0]	93745	1		T7	30		T19	1438		T24	1531
all_values[3]	auto[1]	auto[1]	283970	1		T7	6268		T31	1270		T32	3152
all_values[4]	auto[0]	auto[0]	1156	1		T1	1		T2	1		T17	1
all_values[4]	auto[0]	auto[1]	547	1		T2	1		T4	1		T5	1
all_values[4]	auto[1]	auto[0]	263462	1		T7	5727		T19	1		T24	1
all_values[4]	auto[1]	auto[1]	114212	1		T7	571		T19	1437		T24	1530
all_values[5]	auto[0]	auto[0]	1583	1		T1	1		T2	2		T17	1
all_values[5]	auto[0]	auto[1]	103	1		T8	1		T33	1		T34	1
all_values[5]	auto[1]	auto[0]	377636	1		T7	6298		T19	1438		T24	1531
all_values[5]	auto[1]	auto[1]	55	1		T269	1		T270	2		T271	3