Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	249337	1		T1	1258		T2	100		T4	968
auto[FlashEraseBank]	269305	1		T2	1073		T4	4		T7	206

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	262296	1		T1	632		T2	579		T4	642
auto[FlashOpProgram]	235594	1		T1	313		T2	544		T4	320
auto[FlashOpErase]	16752	1		T1	313		T2	50		T4	10
auto[FlashOpInvalid]	4000	1		T230	200		T135	200		T153	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	262296	1		T1	632		T2	579		T4	642
op[FlashOpProgram]	235594	1		T1	313		T2	544		T4	320
op[FlashOpErase]	16752	1		T1	313		T2	50		T4	10
read_erase_read	628	1		T2	8		T5	1		T59	4
read_prog_read	789	1		T2	2		T6	3		T59	17

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	375647	1		T2	96		T4	388		T6	6
auto[FlashPartInfo]	139570	1		T1	1258		T2	1075		T4	584
auto[FlashPartInfo1]	829	1		T2	1		T9	1		T31	27
auto[FlashPartInfo2]	2596	1		T2	1		T6	1		T19	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190066	1		T2	34		T4	256		T6	5
auto[FlashPartData]	auto[FlashOpProgram]	178022	1		T2	30		T4	128		T6	1
auto[FlashPartData]	auto[FlashOpErase]	3623	1		T2	32		T4	4		T59	21
auto[FlashPartData]	auto[FlashOpInvalid]	3936	1		T230	198		T135	194		T153	198
auto[FlashPartInfo]	auto[FlashOpRead]	69969	1		T1	632		T2	545		T4	386
auto[FlashPartInfo]	auto[FlashOpProgram]	56441	1		T1	313		T2	513		T4	192
auto[FlashPartInfo]	auto[FlashOpErase]	13106	1		T1	313		T2	17		T4	6
auto[FlashPartInfo]	auto[FlashOpInvalid]	54	1		T230	2		T135	6		T146	2
auto[FlashPartInfo1]	auto[FlashOpRead]	659	1		T9	1		T31	27		T43	7
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T146	1		T149	1		T150	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T2	1		T146	1		T149	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T146	2		T149	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1602	1		T6	1		T8	5		T9	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	968	1		T2	1		T19	4		T24	1
auto[FlashPartInfo2]	auto[FlashOpErase]	20	1		T133	1		T153	1		T144	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T153	2		T395	2		T155	2