Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33408	1		T1	644		T2	24		T4	8
auto[1]	43	1		T141	3		T210	1		T34	3
auto[2]	87	1		T65	1		T141	1		T396	2
auto[3]	260	1		T25	1		T26	1		T144	12

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8461	1		T1	161		T2	6		T4	2
evic_idx[1]	8448	1		T1	161		T2	6		T4	2
evic_idx[2]	8447	1		T1	161		T2	6		T4	2
evic_idx[3]	8442	1		T1	161		T2	6		T4	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32760	1		T1	644		T47	700		T36	148
evic_op[2]	289	1		T2	4		T21	1		T25	3

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8121	1		T1	161		T47	175		T36	37
evic_idx[0]	evic_op[1]	auto[1]	9	1		T141	1		T397	2		T398	5
evic_idx[0]	evic_op[1]	auto[2]	11	1		T399	6		T398	1		T400	3
evic_idx[0]	evic_op[1]	auto[3]	61	1		T144	4		T141	6		T142	5
evic_idx[0]	evic_op[2]	auto[0]	59	1		T2	1		T25	1		T207	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T34	1		T401	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T218	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T26	1		T396	1		T35	1
evic_idx[1]	evic_op[1]	auto[0]	8115	1		T1	161		T47	175		T36	37
evic_idx[1]	evic_op[1]	auto[1]	8	1		T141	1		T397	2		T398	5
evic_idx[1]	evic_op[1]	auto[2]	6	1		T399	1		T398	1		T400	2
evic_idx[1]	evic_op[1]	auto[3]	60	1		T144	2		T141	6		T142	4
evic_idx[1]	evic_op[2]	auto[0]	58	1		T2	1		T207	1		T123	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T210	1		T34	1		T402	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T403	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T25	1		T404	1		T405	1
evic_idx[2]	evic_op[1]	auto[0]	8119	1		T1	161		T47	175		T36	37
evic_idx[2]	evic_op[1]	auto[1]	9	1		T141	1		T397	1		T398	5
evic_idx[2]	evic_op[1]	auto[2]	7	1		T399	1		T398	1		T400	2
evic_idx[2]	evic_op[1]	auto[3]	53	1		T144	2		T141	4		T142	3
evic_idx[2]	evic_op[2]	auto[0]	59	1		T2	1		T21	1		T207	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T406	1		T407	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	5	1		T65	1		T396	2		T408	1
evic_idx[2]	evic_op[2]	auto[3]	6	1		T409	1		T289	1		T410	1
evic_idx[3]	evic_op[1]	auto[0]	8115	1		T1	161		T47	175		T36	37
evic_idx[3]	evic_op[1]	auto[1]	6	1		T397	1		T398	3		T411	1
evic_idx[3]	evic_op[1]	auto[2]	7	1		T141	1		T399	2		T398	1
evic_idx[3]	evic_op[1]	auto[3]	53	1		T144	4		T141	3		T142	3
evic_idx[3]	evic_op[2]	auto[0]	61	1		T2	1		T25	1		T22	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T34	1		T412	1		T413	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T402	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	8	1		T319	1		T414	1		T415	1