Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35131	1		T7	2219		T333	15816		T334	1544
rd_lvl[2]	53662	1		T7	978		T333	11448		T116	12400
rd_lvl[3]	19771	1		T7	308		T335	4798		T336	1211
rd_lvl[4]	35640	1		T7	440		T335	4252		T336	5562
rd_lvl[5]	15884	1		T7	163		T138	2456		T337	2426
rd_lvl[6]	23816	1		T7	41		T31	887		T138	2563
rd_lvl[7]	7879	1		T7	151		T31	383		T32	1787
rd_lvl[8]	14913	1		T7	156		T32	1365		T338	3275
rd_lvl[9]	6163	1		T7	247		T338	201		T29	276
rd_lvl[10]	6296	1		T7	60		T29	190		T339	1350
rd_lvl[11]	5646	1		T7	218		T29	1		T339	328
rd_lvl[12]	8945	1		T29	37		T340	1098		T30	631
rd_lvl[13]	2545	1		T341	562		T342	54		T343	135
rd_lvl[14]	6731	1		T7	166		T344	1412		T341	1092
rd_lvl[15]	3156	1		T28	476		T344	354		T291	7