Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	379377	1		T1	1		T2	2		T17	1
all_pins[1]	379377	1		T1	1		T2	2		T17	1
all_pins[2]	379377	1		T1	1		T2	2		T17	1
all_pins[3]	379377	1		T1	1		T2	2		T17	1
all_pins[4]	379377	1		T1	1		T2	2		T17	1
all_pins[5]	379377	1		T1	1		T2	2		T17	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1895173	1		T1	6		T2	12		T17	6
values[0x1]	381089	1		T7	5749		T19	1437		T24	1530
transitions[0x0=>0x1]	343826	1		T7	5177		T19	1437		T24	1530
transitions[0x1=>0x0]	343811	1		T7	5177		T19	1437		T24	1530

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	379229	1		T1	1		T2	2		T17	1
all_pins[0]	values[0x1]	148	1		T269	5		T270	1		T271	2
all_pins[0]	transitions[0x0=>0x1]	75	1		T269	1		T270	1		T271	2
all_pins[0]	transitions[0x1=>0x0]	92	1		T269	2		T270	4		T329	3
all_pins[1]	values[0x0]	379212	1		T1	1		T2	2		T17	1
all_pins[1]	values[0x1]	165	1		T269	6		T270	4		T329	5
all_pins[1]	transitions[0x0=>0x1]	139	1		T269	6		T270	4		T329	5
all_pins[1]	transitions[0x1=>0x0]	3268	1		T28	1096		T349	951		T95	1171
all_pins[2]	values[0x0]	376083	1		T1	1		T2	2		T17	1
all_pins[2]	values[0x1]	3294	1		T28	1096		T349	951		T95	1171
all_pins[2]	transitions[0x0=>0x1]	44	1		T269	1		T270	1		T330	1
all_pins[2]	transitions[0x1=>0x0]	246444	1		T7	5147		T31	1270		T32	3152
all_pins[3]	values[0x0]	129683	1		T1	1		T2	2		T17	1
all_pins[3]	values[0x1]	249694	1		T7	5147		T31	1270		T32	3152
all_pins[3]	transitions[0x0=>0x1]	215830	1		T7	4575		T31	1270		T32	3152
all_pins[3]	transitions[0x1=>0x0]	93869	1		T7	30		T19	1437		T24	1530
all_pins[4]	values[0x0]	251644	1		T1	1		T2	2		T17	1
all_pins[4]	values[0x1]	127733	1		T7	602		T19	1437		T24	1530
all_pins[4]	transitions[0x0=>0x1]	127718	1		T7	602		T19	1437		T24	1530
all_pins[4]	transitions[0x1=>0x0]	40	1		T269	1		T270	2		T271	2
all_pins[5]	values[0x0]	379322	1		T1	1		T2	2		T17	1
all_pins[5]	values[0x1]	55	1		T269	1		T270	2		T271	3
all_pins[5]	transitions[0x0=>0x1]	20	1		T270	1		T271	1		T328	1
all_pins[5]	transitions[0x1=>0x0]	98	1		T269	3		T329	3		T330	2