Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T269	7		T270	4		T271	4
all_values[1]	272	1		T269	7		T270	4		T271	4
all_values[2]	272	1		T269	7		T270	4		T271	4
all_values[3]	272	1		T269	7		T270	4		T271	4
all_values[4]	272	1		T269	7		T270	4		T271	4
all_values[5]	272	1		T269	7		T270	4		T271	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	931	1		T269	23		T270	14		T271	17
auto[1]	701	1		T269	19		T270	10		T271	7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	547	1		T269	13		T270	9		T271	7
auto[1]	1085	1		T269	29		T270	15		T271	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	983	1		T269	24		T270	15		T271	15
auto[1]	649	1		T269	18		T270	9		T271	9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	100	1		T269	2		T270	1		T271	3
all_values[0]	auto[0]	auto[1]	auto[1]	70	1		T269	3		T270	1		T271	1
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T269	1		T270	2		T328	1
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T269	1		T329	2		T330	1
all_values[1]	auto[0]	auto[0]	auto[1]	75	1		T271	2		T328	2		T331	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1		T269	5		T270	2		T329	4
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T269	1		T270	1		T271	2
all_values[1]	auto[1]	auto[1]	auto[1]	47	1		T269	1		T270	1		T328	1
all_values[2]	auto[0]	auto[0]	auto[0]	92	1		T269	5		T270	2		T271	3
all_values[2]	auto[0]	auto[1]	auto[0]	61	1		T270	1		T329	2		T328	2
all_values[2]	auto[1]	auto[0]	auto[1]	63	1		T269	1		T270	1		T271	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T269	1		T329	3		T330	1
all_values[3]	auto[0]	auto[0]	auto[0]	78	1		T269	1		T270	3		T271	2
all_values[3]	auto[0]	auto[1]	auto[0]	89	1		T269	2		T270	1		T271	1
all_values[3]	auto[1]	auto[0]	auto[1]	69	1		T269	3		T330	2		T328	2
all_values[3]	auto[1]	auto[1]	auto[1]	36	1		T269	1		T271	1		T329	2
all_values[4]	auto[0]	auto[0]	auto[0]	74	1		T269	2		T271	1		T329	1
all_values[4]	auto[0]	auto[0]	auto[1]	36	1		T270	1		T271	1		T329	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T269	1		T270	1		T329	2
all_values[4]	auto[0]	auto[1]	auto[1]	20	1		T269	1		T328	2		T332	3
all_values[4]	auto[1]	auto[0]	auto[1]	57	1		T269	2		T271	1		T329	2
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T269	1		T270	2		T271	1
all_values[5]	auto[0]	auto[0]	auto[0]	64	1		T269	1		T270	1		T329	2
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T330	1		T328	1		T332	1
all_values[5]	auto[0]	auto[1]	auto[0]	46	1		T269	1		T329	4		T331	1
all_values[5]	auto[0]	auto[1]	auto[1]	17	1		T270	1		T271	1		T328	2
all_values[5]	auto[1]	auto[0]	auto[1]	76	1		T269	4		T270	2		T271	1
all_values[5]	auto[1]	auto[1]	auto[1]	41	1		T269	1		T271	2		T328	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal