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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.70 94.02 98.31 91.84 98.17 96.89 98.24


Total test records in report: 1256
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T1075 /workspace/coverage/default/8.flash_ctrl_wo.3795561426 Aug 12 06:40:14 PM PDT 24 Aug 12 06:43:35 PM PDT 24 5873602600 ps
T1076 /workspace/coverage/default/1.flash_ctrl_prog_reset.3165892190 Aug 12 06:39:26 PM PDT 24 Aug 12 06:42:21 PM PDT 24 9589143000 ps
T1077 /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.592894314 Aug 12 06:41:03 PM PDT 24 Aug 12 06:41:17 PM PDT 24 36055500 ps
T1078 /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3156311144 Aug 12 06:42:41 PM PDT 24 Aug 12 06:45:54 PM PDT 24 15822122800 ps
T1079 /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3776962877 Aug 12 06:41:05 PM PDT 24 Aug 12 06:42:03 PM PDT 24 10065555800 ps
T1080 /workspace/coverage/default/8.flash_ctrl_mp_regions.826918143 Aug 12 06:40:10 PM PDT 24 Aug 12 06:44:58 PM PDT 24 11616005900 ps
T1081 /workspace/coverage/default/23.flash_ctrl_sec_info_access.2815526529 Aug 12 06:41:46 PM PDT 24 Aug 12 06:42:59 PM PDT 24 1867901200 ps
T1082 /workspace/coverage/default/73.flash_ctrl_otp_reset.1157300725 Aug 12 06:43:34 PM PDT 24 Aug 12 06:45:49 PM PDT 24 37742400 ps
T1083 /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2849701178 Aug 12 06:41:04 PM PDT 24 Aug 12 06:43:44 PM PDT 24 14858429400 ps
T1084 /workspace/coverage/default/43.flash_ctrl_smoke.746560356 Aug 12 06:43:02 PM PDT 24 Aug 12 06:44:15 PM PDT 24 43563300 ps
T1085 /workspace/coverage/default/12.flash_ctrl_rw.770128328 Aug 12 06:40:32 PM PDT 24 Aug 12 06:50:34 PM PDT 24 3811574100 ps
T1086 /workspace/coverage/default/2.flash_ctrl_connect.3825385744 Aug 12 06:39:44 PM PDT 24 Aug 12 06:40:00 PM PDT 24 51234600 ps
T1087 /workspace/coverage/default/12.flash_ctrl_re_evict.1729383867 Aug 12 06:40:33 PM PDT 24 Aug 12 06:41:06 PM PDT 24 262796600 ps
T1088 /workspace/coverage/default/2.flash_ctrl_hw_rma.4115238120 Aug 12 06:39:23 PM PDT 24 Aug 12 07:13:17 PM PDT 24 334103484300 ps
T1089 /workspace/coverage/default/67.flash_ctrl_connect.450501150 Aug 12 06:43:24 PM PDT 24 Aug 12 06:43:40 PM PDT 24 14811700 ps
T1090 /workspace/coverage/default/48.flash_ctrl_smoke.1700997764 Aug 12 06:43:14 PM PDT 24 Aug 12 06:44:05 PM PDT 24 71532400 ps
T1091 /workspace/coverage/default/8.flash_ctrl_disable.1075747432 Aug 12 06:40:10 PM PDT 24 Aug 12 06:40:32 PM PDT 24 26660500 ps
T1092 /workspace/coverage/default/58.flash_ctrl_connect.3331173098 Aug 12 06:43:26 PM PDT 24 Aug 12 06:43:40 PM PDT 24 22371300 ps
T1093 /workspace/coverage/default/34.flash_ctrl_smoke.1683120779 Aug 12 06:42:54 PM PDT 24 Aug 12 06:44:34 PM PDT 24 75343100 ps
T1094 /workspace/coverage/default/3.flash_ctrl_sw_op.1234096364 Aug 12 06:39:43 PM PDT 24 Aug 12 06:40:10 PM PDT 24 28646100 ps
T1095 /workspace/coverage/default/10.flash_ctrl_sec_info_access.1978727419 Aug 12 06:40:25 PM PDT 24 Aug 12 06:41:29 PM PDT 24 1183662300 ps
T61 /workspace/coverage/default/2.flash_ctrl_sec_cm.2392695278 Aug 12 06:39:25 PM PDT 24 Aug 12 08:00:55 PM PDT 24 3825643400 ps
T46 /workspace/coverage/default/0.flash_ctrl_access_after_disable.2882085236 Aug 12 06:39:36 PM PDT 24 Aug 12 06:39:49 PM PDT 24 13738100 ps
T1096 /workspace/coverage/default/13.flash_ctrl_smoke.3002492230 Aug 12 06:40:35 PM PDT 24 Aug 12 06:42:41 PM PDT 24 37440400 ps
T1097 /workspace/coverage/default/15.flash_ctrl_invalid_op.1941864510 Aug 12 06:40:54 PM PDT 24 Aug 12 06:42:22 PM PDT 24 990127200 ps
T1098 /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.837876017 Aug 12 06:39:54 PM PDT 24 Aug 12 06:53:24 PM PDT 24 160155511000 ps
T1099 /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3996637847 Aug 12 06:40:19 PM PDT 24 Aug 12 06:55:25 PM PDT 24 160198533800 ps
T1100 /workspace/coverage/default/28.flash_ctrl_alert_test.1026473016 Aug 12 06:42:09 PM PDT 24 Aug 12 06:42:23 PM PDT 24 48260600 ps
T1101 /workspace/coverage/default/44.flash_ctrl_connect.1977831329 Aug 12 06:43:01 PM PDT 24 Aug 12 06:43:15 PM PDT 24 15539700 ps
T1102 /workspace/coverage/default/45.flash_ctrl_sec_info_access.278888311 Aug 12 06:43:02 PM PDT 24 Aug 12 06:44:17 PM PDT 24 4287172600 ps
T1103 /workspace/coverage/default/13.flash_ctrl_rw.3292155299 Aug 12 06:40:45 PM PDT 24 Aug 12 06:50:30 PM PDT 24 4503605000 ps
T1104 /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1119145532 Aug 12 06:39:29 PM PDT 24 Aug 12 07:27:48 PM PDT 24 256307320600 ps
T1105 /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.4152410481 Aug 12 06:42:55 PM PDT 24 Aug 12 06:47:29 PM PDT 24 5229246400 ps
T1106 /workspace/coverage/default/4.flash_ctrl_rw_serr.2153893315 Aug 12 06:39:50 PM PDT 24 Aug 12 06:43:47 PM PDT 24 1753474900 ps
T1107 /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3184882785 Aug 12 06:40:55 PM PDT 24 Aug 12 06:41:24 PM PDT 24 71038900 ps
T1108 /workspace/coverage/default/22.flash_ctrl_prog_reset.3300284202 Aug 12 06:41:38 PM PDT 24 Aug 12 06:41:52 PM PDT 24 19199100 ps
T1109 /workspace/coverage/default/9.flash_ctrl_connect.569160276 Aug 12 06:40:20 PM PDT 24 Aug 12 06:40:36 PM PDT 24 50626200 ps
T1110 /workspace/coverage/default/33.flash_ctrl_smoke.997969017 Aug 12 06:42:42 PM PDT 24 Aug 12 06:45:11 PM PDT 24 59325400 ps
T1111 /workspace/coverage/default/0.flash_ctrl_wo.735848481 Aug 12 06:39:17 PM PDT 24 Aug 12 06:42:27 PM PDT 24 5475597300 ps
T1112 /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2680707000 Aug 12 06:39:26 PM PDT 24 Aug 12 06:40:22 PM PDT 24 10035029300 ps
T1113 /workspace/coverage/default/47.flash_ctrl_smoke.302439010 Aug 12 06:43:16 PM PDT 24 Aug 12 06:44:34 PM PDT 24 24068400 ps
T1114 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1104108609 Aug 12 06:38:49 PM PDT 24 Aug 12 06:39:02 PM PDT 24 13685600 ps
T70 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.180135109 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:29 PM PDT 24 109818600 ps
T71 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.226107718 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:31 PM PDT 24 666997700 ps
T1115 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1806762854 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:06 PM PDT 24 12233500 ps
T72 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3347081824 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:37 PM PDT 24 65544700 ps
T103 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1948713506 Aug 12 06:39:08 PM PDT 24 Aug 12 06:54:23 PM PDT 24 1069136300 ps
T266 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4286033352 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:59 PM PDT 24 636346200 ps
T209 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2049622379 Aug 12 06:38:53 PM PDT 24 Aug 12 06:40:11 PM PDT 24 7465613600 ps
T255 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1687203080 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:08 PM PDT 24 312312800 ps
T256 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2342185913 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:26 PM PDT 24 92002700 ps
T106 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1587640960 Aug 12 06:39:09 PM PDT 24 Aug 12 06:39:26 PM PDT 24 74527000 ps
T257 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.175131955 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:28 PM PDT 24 254503900 ps
T107 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1025897023 Aug 12 06:39:00 PM PDT 24 Aug 12 06:39:20 PM PDT 24 331866200 ps
T269 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2434395625 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:33 PM PDT 24 18361700 ps
T104 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3699588412 Aug 12 06:38:52 PM PDT 24 Aug 12 06:46:22 PM PDT 24 473484500 ps
T105 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3767803844 Aug 12 06:38:47 PM PDT 24 Aug 12 06:51:20 PM PDT 24 362980100 ps
T305 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2577737049 Aug 12 06:39:03 PM PDT 24 Aug 12 06:40:05 PM PDT 24 5900190600 ps
T208 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1726959698 Aug 12 06:38:47 PM PDT 24 Aug 12 06:39:07 PM PDT 24 931521000 ps
T270 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.916098206 Aug 12 06:39:24 PM PDT 24 Aug 12 06:39:37 PM PDT 24 109326000 ps
T1116 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.465852695 Aug 12 06:38:53 PM PDT 24 Aug 12 06:39:33 PM PDT 24 1282896900 ps
T271 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1811727152 Aug 12 06:39:11 PM PDT 24 Aug 12 06:39:24 PM PDT 24 18453400 ps
T242 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.805966146 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:50 PM PDT 24 69308600 ps
T1117 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.239415958 Aug 12 06:39:04 PM PDT 24 Aug 12 06:39:20 PM PDT 24 11638300 ps
T1118 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.821021301 Aug 12 06:38:57 PM PDT 24 Aug 12 06:39:11 PM PDT 24 12657100 ps
T258 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2740735994 Aug 12 06:39:17 PM PDT 24 Aug 12 06:39:34 PM PDT 24 96666600 ps
T243 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2885906654 Aug 12 06:39:08 PM PDT 24 Aug 12 06:39:27 PM PDT 24 91356800 ps
T275 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1568048069 Aug 12 06:38:38 PM PDT 24 Aug 12 06:39:09 PM PDT 24 32291500 ps
T1119 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2193778241 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:04 PM PDT 24 41594700 ps
T248 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.683827687 Aug 12 06:39:17 PM PDT 24 Aug 12 06:46:49 PM PDT 24 675044400 ps
T1120 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.171411715 Aug 12 06:38:43 PM PDT 24 Aug 12 06:38:56 PM PDT 24 23874500 ps
T259 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1095429021 Aug 12 06:39:13 PM PDT 24 Aug 12 06:39:36 PM PDT 24 924591300 ps
T260 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2545343092 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:09 PM PDT 24 59560100 ps
T249 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.902009588 Aug 12 06:39:19 PM PDT 24 Aug 12 06:46:56 PM PDT 24 1445328000 ps
T244 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2917584198 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:08 PM PDT 24 118770100 ps
T1121 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.352780778 Aug 12 06:38:30 PM PDT 24 Aug 12 06:39:17 PM PDT 24 1187006700 ps
T245 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3725134103 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:38 PM PDT 24 364076500 ps
T1122 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2608258026 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:15 PM PDT 24 14017500 ps
T329 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2954518060 Aug 12 06:39:33 PM PDT 24 Aug 12 06:39:46 PM PDT 24 17283900 ps
T261 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3528867314 Aug 12 06:39:03 PM PDT 24 Aug 12 06:39:21 PM PDT 24 48577800 ps
T1123 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1118802347 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:35 PM PDT 24 17611400 ps
T246 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1602180871 Aug 12 06:38:57 PM PDT 24 Aug 12 06:39:13 PM PDT 24 48501700 ps
T330 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2782702130 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:34 PM PDT 24 17350600 ps
T328 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3694651420 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:20 PM PDT 24 15285300 ps
T1124 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3497855871 Aug 12 06:39:06 PM PDT 24 Aug 12 06:39:20 PM PDT 24 34075300 ps
T247 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3306093808 Aug 12 06:39:02 PM PDT 24 Aug 12 06:39:19 PM PDT 24 220256600 ps
T274 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3220699808 Aug 12 06:39:05 PM PDT 24 Aug 12 06:46:51 PM PDT 24 684423700 ps
T272 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3541170134 Aug 12 06:39:09 PM PDT 24 Aug 12 06:39:28 PM PDT 24 114311100 ps
T281 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1648584033 Aug 12 06:38:59 PM PDT 24 Aug 12 06:53:53 PM PDT 24 781234300 ps
T278 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2997986592 Aug 12 06:39:42 PM PDT 24 Aug 12 06:40:02 PM PDT 24 125873700 ps
T331 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3801383410 Aug 12 06:39:21 PM PDT 24 Aug 12 06:39:35 PM PDT 24 20740100 ps
T332 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.786436997 Aug 12 06:39:36 PM PDT 24 Aug 12 06:39:49 PM PDT 24 50996000 ps
T1125 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1015718132 Aug 12 06:39:05 PM PDT 24 Aug 12 06:39:19 PM PDT 24 24327400 ps
T1126 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2860499525 Aug 12 06:38:50 PM PDT 24 Aug 12 06:40:08 PM PDT 24 8774692900 ps
T1127 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2883465074 Aug 12 06:39:10 PM PDT 24 Aug 12 06:39:28 PM PDT 24 82364500 ps
T1128 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2818048364 Aug 12 06:38:56 PM PDT 24 Aug 12 06:39:10 PM PDT 24 31009300 ps
T1129 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1546548526 Aug 12 06:39:18 PM PDT 24 Aug 12 06:39:34 PM PDT 24 75175200 ps
T1130 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2218730087 Aug 12 06:39:22 PM PDT 24 Aug 12 06:39:35 PM PDT 24 23409800 ps
T1131 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2365856940 Aug 12 06:39:18 PM PDT 24 Aug 12 06:39:34 PM PDT 24 97579900 ps
T351 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2050039198 Aug 12 06:39:11 PM PDT 24 Aug 12 06:46:54 PM PDT 24 2299838300 ps
T306 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4151022075 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:38 PM PDT 24 306054200 ps
T1132 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2577218789 Aug 12 06:39:08 PM PDT 24 Aug 12 06:39:21 PM PDT 24 29692800 ps
T1133 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.325731955 Aug 12 06:39:22 PM PDT 24 Aug 12 06:39:35 PM PDT 24 48576600 ps
T1134 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1932336580 Aug 12 06:39:24 PM PDT 24 Aug 12 06:39:37 PM PDT 24 18139900 ps
T1135 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3372446369 Aug 12 06:39:15 PM PDT 24 Aug 12 06:39:28 PM PDT 24 43235200 ps
T1136 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1400422612 Aug 12 06:39:11 PM PDT 24 Aug 12 06:39:24 PM PDT 24 16971600 ps
T1137 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1434637411 Aug 12 06:38:54 PM PDT 24 Aug 12 06:39:09 PM PDT 24 38457500 ps
T1138 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4126761267 Aug 12 06:38:52 PM PDT 24 Aug 12 06:39:08 PM PDT 24 14297800 ps
T1139 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1417353336 Aug 12 06:39:08 PM PDT 24 Aug 12 06:39:23 PM PDT 24 26412900 ps
T282 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3222658102 Aug 12 06:38:53 PM PDT 24 Aug 12 06:39:12 PM PDT 24 137101000 ps
T1140 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2494101111 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:13 PM PDT 24 146582600 ps
T1141 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3161365641 Aug 12 06:39:08 PM PDT 24 Aug 12 06:39:24 PM PDT 24 22249000 ps
T307 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4113487839 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:22 PM PDT 24 279566900 ps
T308 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.175563221 Aug 12 06:38:50 PM PDT 24 Aug 12 06:54:08 PM PDT 24 3283230300 ps
T1142 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2296961090 Aug 12 06:38:48 PM PDT 24 Aug 12 06:39:04 PM PDT 24 37081500 ps
T1143 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.528019118 Aug 12 06:38:54 PM PDT 24 Aug 12 06:39:07 PM PDT 24 17236100 ps
T1144 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3589583564 Aug 12 06:38:55 PM PDT 24 Aug 12 06:39:11 PM PDT 24 63857200 ps
T309 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.918643962 Aug 12 06:39:05 PM PDT 24 Aug 12 06:39:24 PM PDT 24 147794900 ps
T1145 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1298550401 Aug 12 06:39:02 PM PDT 24 Aug 12 06:39:25 PM PDT 24 35829100 ps
T310 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2307849642 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:53 PM PDT 24 55001900 ps
T267 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3598385639 Aug 12 06:39:03 PM PDT 24 Aug 12 06:39:23 PM PDT 24 201647700 ps
T357 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3711116218 Aug 12 06:38:46 PM PDT 24 Aug 12 06:45:07 PM PDT 24 174645400 ps
T1146 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1866610383 Aug 12 06:38:48 PM PDT 24 Aug 12 06:39:34 PM PDT 24 214174700 ps
T1147 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3037033074 Aug 12 06:39:29 PM PDT 24 Aug 12 06:39:43 PM PDT 24 15314100 ps
T250 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3520704781 Aug 12 06:38:40 PM PDT 24 Aug 12 06:38:53 PM PDT 24 15809300 ps
T350 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1585981370 Aug 12 06:38:46 PM PDT 24 Aug 12 06:51:26 PM PDT 24 856385400 ps
T1148 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3365424636 Aug 12 06:39:31 PM PDT 24 Aug 12 06:39:45 PM PDT 24 16171500 ps
T1149 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2632958094 Aug 12 06:39:17 PM PDT 24 Aug 12 06:39:30 PM PDT 24 31586700 ps
T1150 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.4123574249 Aug 12 06:39:28 PM PDT 24 Aug 12 06:39:42 PM PDT 24 157054200 ps
T1151 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1616983632 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:33 PM PDT 24 49990900 ps
T1152 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3108561410 Aug 12 06:39:23 PM PDT 24 Aug 12 06:39:37 PM PDT 24 28882400 ps
T1153 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3824736593 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:15 PM PDT 24 32763300 ps
T1154 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2138026904 Aug 12 06:38:45 PM PDT 24 Aug 12 06:39:01 PM PDT 24 15813000 ps
T312 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3507360988 Aug 12 06:38:53 PM PDT 24 Aug 12 06:39:11 PM PDT 24 107023300 ps
T251 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1007733802 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:05 PM PDT 24 92772600 ps
T311 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2410889636 Aug 12 06:38:42 PM PDT 24 Aug 12 06:39:20 PM PDT 24 190305000 ps
T1155 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1537600513 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:28 PM PDT 24 2057801700 ps
T268 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2333386415 Aug 12 06:39:11 PM PDT 24 Aug 12 06:39:30 PM PDT 24 58151500 ps
T1156 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.474509725 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:15 PM PDT 24 173962500 ps
T1157 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2000382411 Aug 12 06:39:23 PM PDT 24 Aug 12 06:39:37 PM PDT 24 47633700 ps
T1158 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.907258881 Aug 12 06:39:16 PM PDT 24 Aug 12 06:39:30 PM PDT 24 15230500 ps
T353 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3000368843 Aug 12 06:39:03 PM PDT 24 Aug 12 06:46:44 PM PDT 24 2393274300 ps
T1159 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2704806319 Aug 12 06:39:18 PM PDT 24 Aug 12 06:39:32 PM PDT 24 231079700 ps
T1160 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1636579174 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:04 PM PDT 24 14304400 ps
T1161 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3258857524 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:13 PM PDT 24 106822100 ps
T1162 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2089359130 Aug 12 06:39:06 PM PDT 24 Aug 12 06:39:40 PM PDT 24 226365000 ps
T1163 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.178452003 Aug 12 06:39:16 PM PDT 24 Aug 12 06:39:29 PM PDT 24 164706500 ps
T356 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2857163122 Aug 12 06:38:50 PM PDT 24 Aug 12 06:45:17 PM PDT 24 413973200 ps
T1164 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2068990319 Aug 12 06:39:18 PM PDT 24 Aug 12 06:39:36 PM PDT 24 162234500 ps
T1165 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4003817156 Aug 12 06:38:55 PM PDT 24 Aug 12 06:39:08 PM PDT 24 22167300 ps
T276 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1879120106 Aug 12 06:39:11 PM PDT 24 Aug 12 06:39:31 PM PDT 24 113651700 ps
T252 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1593740734 Aug 12 06:38:47 PM PDT 24 Aug 12 06:39:01 PM PDT 24 113311500 ps
T1166 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3254214749 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:33 PM PDT 24 17440500 ps
T1167 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3652180912 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:38 PM PDT 24 28436100 ps
T277 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2656008534 Aug 12 06:38:45 PM PDT 24 Aug 12 06:39:02 PM PDT 24 54341200 ps
T1168 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.106904890 Aug 12 06:39:22 PM PDT 24 Aug 12 06:39:39 PM PDT 24 98544100 ps
T1169 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.89434732 Aug 12 06:38:41 PM PDT 24 Aug 12 06:38:57 PM PDT 24 11850700 ps
T1170 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.733629658 Aug 12 06:39:17 PM PDT 24 Aug 12 06:39:35 PM PDT 24 71460000 ps
T1171 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.756878533 Aug 12 06:39:25 PM PDT 24 Aug 12 06:39:38 PM PDT 24 45870600 ps
T1172 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3128887546 Aug 12 06:38:31 PM PDT 24 Aug 12 06:39:05 PM PDT 24 105581500 ps
T1173 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3656851049 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:33 PM PDT 24 72165300 ps
T283 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4229202551 Aug 12 06:39:13 PM PDT 24 Aug 12 06:54:10 PM PDT 24 1163322000 ps
T1174 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3631772486 Aug 12 06:38:53 PM PDT 24 Aug 12 06:39:07 PM PDT 24 28345800 ps
T1175 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.305978492 Aug 12 06:38:56 PM PDT 24 Aug 12 06:39:32 PM PDT 24 631139600 ps
T1176 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2293911718 Aug 12 06:39:23 PM PDT 24 Aug 12 06:39:37 PM PDT 24 19162900 ps
T1177 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2464202165 Aug 12 06:38:44 PM PDT 24 Aug 12 06:46:17 PM PDT 24 685088200 ps
T1178 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3326708784 Aug 12 06:39:03 PM PDT 24 Aug 12 06:39:16 PM PDT 24 14373300 ps
T1179 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.267296094 Aug 12 06:38:52 PM PDT 24 Aug 12 06:39:09 PM PDT 24 14187500 ps
T1180 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3746616557 Aug 12 06:39:08 PM PDT 24 Aug 12 06:39:21 PM PDT 24 30112700 ps
T1181 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3739277338 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:04 PM PDT 24 25327400 ps
T1182 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3232285490 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:21 PM PDT 24 16124600 ps
T1183 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1817791677 Aug 12 06:38:30 PM PDT 24 Aug 12 06:38:49 PM PDT 24 86588800 ps
T354 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.570844392 Aug 12 06:39:10 PM PDT 24 Aug 12 06:54:19 PM PDT 24 949746200 ps
T1184 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2340722817 Aug 12 06:39:34 PM PDT 24 Aug 12 06:39:47 PM PDT 24 15376400 ps
T1185 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.14918746 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:35 PM PDT 24 153977600 ps
T280 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.350003545 Aug 12 06:39:16 PM PDT 24 Aug 12 06:39:32 PM PDT 24 43245400 ps
T1186 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2570223568 Aug 12 06:39:39 PM PDT 24 Aug 12 06:39:53 PM PDT 24 16205300 ps
T1187 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.233263166 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:05 PM PDT 24 44331000 ps
T273 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.991955349 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:08 PM PDT 24 139553500 ps
T1188 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.144478793 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:28 PM PDT 24 14853200 ps
T253 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3668416562 Aug 12 06:38:48 PM PDT 24 Aug 12 06:39:02 PM PDT 24 19451000 ps
T1189 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1484637489 Aug 12 06:39:02 PM PDT 24 Aug 12 06:39:18 PM PDT 24 24121500 ps
T1190 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1444517683 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:29 PM PDT 24 120764800 ps
T1191 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3490383339 Aug 12 06:39:05 PM PDT 24 Aug 12 06:39:18 PM PDT 24 25271600 ps
T1192 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2222067436 Aug 12 06:39:13 PM PDT 24 Aug 12 06:39:27 PM PDT 24 61323100 ps
T1193 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.364607734 Aug 12 06:39:04 PM PDT 24 Aug 12 06:39:17 PM PDT 24 21482300 ps
T1194 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2760156010 Aug 12 06:39:03 PM PDT 24 Aug 12 06:39:19 PM PDT 24 59951300 ps
T1195 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.377887070 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:04 PM PDT 24 57983700 ps
T1196 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2758143666 Aug 12 06:39:18 PM PDT 24 Aug 12 06:39:31 PM PDT 24 88086900 ps
T1197 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.690270773 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:22 PM PDT 24 182936000 ps
T1198 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1800286875 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:36 PM PDT 24 123727300 ps
T1199 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.930203504 Aug 12 06:39:17 PM PDT 24 Aug 12 06:39:34 PM PDT 24 97450500 ps
T313 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3206530005 Aug 12 06:38:44 PM PDT 24 Aug 12 06:39:06 PM PDT 24 304984500 ps
T1200 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3667244770 Aug 12 06:38:44 PM PDT 24 Aug 12 06:38:58 PM PDT 24 16672400 ps
T1201 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.4209956321 Aug 12 06:38:49 PM PDT 24 Aug 12 06:39:05 PM PDT 24 34380600 ps
T1202 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.224052196 Aug 12 06:39:23 PM PDT 24 Aug 12 06:39:36 PM PDT 24 28222100 ps
T1203 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4079747855 Aug 12 06:39:21 PM PDT 24 Aug 12 06:39:38 PM PDT 24 19714200 ps
T355 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1834779584 Aug 12 06:39:14 PM PDT 24 Aug 12 06:46:58 PM PDT 24 4241104700 ps
T1204 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.595511311 Aug 12 06:38:46 PM PDT 24 Aug 12 06:39:01 PM PDT 24 370603900 ps
T1205 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.858070084 Aug 12 06:38:56 PM PDT 24 Aug 12 06:39:13 PM PDT 24 54674300 ps
T1206 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.762092496 Aug 12 06:39:15 PM PDT 24 Aug 12 06:39:31 PM PDT 24 11030700 ps
T1207 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3017579572 Aug 12 06:39:11 PM PDT 24 Aug 12 06:39:26 PM PDT 24 130109400 ps
T1208 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1304298451 Aug 12 06:39:13 PM PDT 24 Aug 12 06:39:27 PM PDT 24 108862700 ps
T1209 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.737918913 Aug 12 06:39:00 PM PDT 24 Aug 12 06:39:14 PM PDT 24 54183000 ps
T279 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3399775590 Aug 12 06:39:22 PM PDT 24 Aug 12 06:39:42 PM PDT 24 66022200 ps
T1210 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1077260989 Aug 12 06:39:09 PM PDT 24 Aug 12 06:39:25 PM PDT 24 12333000 ps
T1211 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.366200924 Aug 12 06:38:50 PM PDT 24 Aug 12 06:39:10 PM PDT 24 181662700 ps
T1212 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2058103193 Aug 12 06:39:09 PM PDT 24 Aug 12 06:39:24 PM PDT 24 64681400 ps
T1213 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.332390185 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:40 PM PDT 24 66829600 ps
T1214 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.203461623 Aug 12 06:39:05 PM PDT 24 Aug 12 06:39:21 PM PDT 24 31317100 ps
T314 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2898275938 Aug 12 06:39:08 PM PDT 24 Aug 12 06:39:26 PM PDT 24 496745500 ps
T1215 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3730911712 Aug 12 06:38:57 PM PDT 24 Aug 12 06:45:25 PM PDT 24 1706536300 ps
T315 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.676279914 Aug 12 06:38:53 PM PDT 24 Aug 12 06:39:12 PM PDT 24 136081700 ps
T1216 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4044466466 Aug 12 06:39:05 PM PDT 24 Aug 12 06:39:21 PM PDT 24 112789300 ps
T1217 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.317004942 Aug 12 06:39:27 PM PDT 24 Aug 12 06:39:44 PM PDT 24 83797500 ps
T352 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1996894428 Aug 12 06:39:20 PM PDT 24 Aug 12 06:54:35 PM PDT 24 747129300 ps
T1218 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2089790203 Aug 12 06:38:56 PM PDT 24 Aug 12 06:40:17 PM PDT 24 3146944400 ps
T1219 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.963368023 Aug 12 06:39:22 PM PDT 24 Aug 12 06:39:35 PM PDT 24 15685500 ps
T1220 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.9423991 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:25 PM PDT 24 52122900 ps
T1221 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3643703513 Aug 12 06:39:09 PM PDT 24 Aug 12 06:39:27 PM PDT 24 26315900 ps
T1222 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1098465161 Aug 12 06:38:49 PM PDT 24 Aug 12 06:39:03 PM PDT 24 16524000 ps
T1223 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3941838473 Aug 12 06:38:47 PM PDT 24 Aug 12 06:39:03 PM PDT 24 17729400 ps
T1224 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1337069069 Aug 12 06:38:53 PM PDT 24 Aug 12 06:39:09 PM PDT 24 11645300 ps
T1225 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1983546854 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:17 PM PDT 24 40984300 ps
T1226 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3471272014 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:29 PM PDT 24 49223800 ps
T1227 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.275140092 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:21 PM PDT 24 88703500 ps
T1228 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1562343664 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:07 PM PDT 24 73068500 ps
T1229 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3088261318 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:30 PM PDT 24 217458200 ps
T1230 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2062119383 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:33 PM PDT 24 14650200 ps
T1231 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1831937658 Aug 12 06:39:01 PM PDT 24 Aug 12 06:39:17 PM PDT 24 199537700 ps
T1232 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3876416316 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:16 PM PDT 24 53773100 ps
T1233 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1445837315 Aug 12 06:39:05 PM PDT 24 Aug 12 06:39:18 PM PDT 24 28282400 ps
T1234 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2402304680 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:33 PM PDT 24 16834000 ps
T1235 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1545879229 Aug 12 06:38:55 PM PDT 24 Aug 12 06:39:15 PM PDT 24 141822700 ps
T1236 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.583181489 Aug 12 06:39:01 PM PDT 24 Aug 12 06:46:42 PM PDT 24 350467600 ps
T1237 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3651987289 Aug 12 06:39:02 PM PDT 24 Aug 12 06:39:15 PM PDT 24 26461900 ps
T1238 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2398404811 Aug 12 06:38:51 PM PDT 24 Aug 12 06:39:08 PM PDT 24 42102100 ps
T1239 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.319114043 Aug 12 06:39:10 PM PDT 24 Aug 12 06:39:24 PM PDT 24 15876500 ps
T254 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4288352224 Aug 12 06:38:40 PM PDT 24 Aug 12 06:38:53 PM PDT 24 29653500 ps
T1240 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3465075137 Aug 12 06:38:54 PM PDT 24 Aug 12 06:39:07 PM PDT 24 18943200 ps
T1241 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2342928133 Aug 12 06:38:49 PM PDT 24 Aug 12 06:39:24 PM PDT 24 752461400 ps
T1242 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1035811412 Aug 12 06:38:57 PM PDT 24 Aug 12 06:39:34 PM PDT 24 731130200 ps
T1243 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.711134481 Aug 12 06:39:17 PM PDT 24 Aug 12 06:39:31 PM PDT 24 18378700 ps
T1244 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3034154059 Aug 12 06:39:21 PM PDT 24 Aug 12 06:39:35 PM PDT 24 16647700 ps
T1245 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3960514501 Aug 12 06:39:19 PM PDT 24 Aug 12 06:39:38 PM PDT 24 513027600 ps
T1246 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2246644305 Aug 12 06:39:16 PM PDT 24 Aug 12 06:39:30 PM PDT 24 12370300 ps
T1247 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1382771919 Aug 12 06:39:20 PM PDT 24 Aug 12 06:39:34 PM PDT 24 16635300 ps
T1248 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1144079657 Aug 12 06:39:07 PM PDT 24 Aug 12 06:39:25 PM PDT 24 208475000 ps
T1249 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4234625601 Aug 12 06:38:35 PM PDT 24 Aug 12 06:38:48 PM PDT 24 29806300 ps
T1250 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1962191280 Aug 12 06:38:55 PM PDT 24 Aug 12 06:39:12 PM PDT 24 362867500 ps
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