Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	366082	1		T1	2		T2	1		T3	3293
all_values[1]	366082	1		T1	2		T2	1		T3	3293
all_values[2]	366082	1		T1	2		T2	1		T3	3293
all_values[3]	366082	1		T1	2		T2	1		T3	3293
all_values[4]	366082	1		T1	2		T2	1		T3	3293
all_values[5]	366082	1		T1	2		T2	1		T3	3293

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	738445	1		T1	12		T2	6		T3	6590
auto[1]	1458047	1		T3	13168		T6	6596		T19	9760

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1068629	1		T1	7		T2	4		T3	9880
auto[1]	1127863	1		T1	5		T2	2		T3	9878

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	365907	1		T1	2		T2	1		T3	3293
all_values[0]	auto[1]	auto[1]	175	1		T264	1		T265	1		T266	3
all_values[1]	auto[0]	auto[1]	365908	1		T1	2		T2	1		T3	3293
all_values[1]	auto[1]	auto[1]	174	1		T264	4		T265	4		T266	5
all_values[2]	auto[0]	auto[0]	1569	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	69	1		T264	1		T265	1		T312	2
all_values[2]	auto[1]	auto[0]	364383	1		T3	3292		T6	1649		T19	2440
all_values[2]	auto[1]	auto[1]	61	1		T264	1		T265	1		T266	2
all_values[3]	auto[0]	auto[0]	1611	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	64	1		T264	1		T266	1		T312	1
all_values[3]	auto[1]	auto[0]	78180	1		T3	1646		T6	547		T19	1199
all_values[3]	auto[1]	auto[1]	286227	1		T3	1646		T6	1102		T19	1241
all_values[4]	auto[0]	auto[0]	1119	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	549	1		T1	1		T5	1		T14	1
all_values[4]	auto[1]	auto[0]	255838	1		T3	1646		T6	1098		T19	1199
all_values[4]	auto[1]	auto[1]	108576	1		T3	1646		T6	551		T19	1241
all_values[5]	auto[0]	auto[0]	1557	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	92	1		T14	1		T28	1		T29	1
all_values[5]	auto[1]	auto[0]	364372	1		T3	3292		T6	1649		T19	2440
all_values[5]	auto[1]	auto[1]	61	1		T312	1		T313	3		T314	2