Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	247106	1		T1	13		T2	1		T3	688
auto[FlashEraseBank]	270250	1		T3	958		T5	36		T6	247

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	261672	1		T1	3		T2	1		T3	1646
auto[FlashOpProgram]	234826	1		T1	4		T5	99		T15	2273
auto[FlashOpErase]	16858	1		T1	6		T5	26		T30	2
auto[FlashOpInvalid]	4000	1		T150	200		T113	200		T129	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	261672	1		T1	3		T2	1		T3	1646
op[FlashOpProgram]	234826	1		T1	4		T5	99		T15	2273
op[FlashOpErase]	16858	1		T1	6		T5	26		T30	2
read_erase_read	574	1		T1	1		T5	2		T30	2
read_prog_read	805	1		T5	14		T15	8		T30	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	372387	1		T1	13		T2	1		T3	1646
auto[FlashPartInfo]	140972	1		T5	3		T6	551		T14	191
auto[FlashPartInfo1]	904	1		T14	3		T15	1		T71	1
auto[FlashPartInfo2]	3093	1		T5	1		T14	4		T15	11

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189828	1		T1	3		T2	1		T3	1646
auto[FlashPartData]	auto[FlashOpProgram]	175055	1		T1	4		T5	96		T15	2006
auto[FlashPartData]	auto[FlashOpErase]	3580	1		T1	6		T5	26		T30	2
auto[FlashPartData]	auto[FlashOpInvalid]	3924	1		T150	196		T113	194		T129	198
auto[FlashPartInfo]	auto[FlashOpRead]	69059	1		T5	1		T6	551		T14	191
auto[FlashPartInfo]	auto[FlashOpProgram]	58615	1		T5	2		T15	261		T28	100
auto[FlashPartInfo]	auto[FlashOpErase]	13240	1		T24	9		T25	9		T26	4
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T113	4		T129	2		T223	2
auto[FlashPartInfo1]	auto[FlashOpRead]	729	1		T14	3		T15	1		T71	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T113	1		T139	32		T390	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T62	1		T113	1		T114	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T113	2		T116	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2056	1		T14	4		T15	5		T28	8
auto[FlashPartInfo2]	auto[FlashOpProgram]	991	1		T5	1		T15	6		T28	2
auto[FlashPartInfo2]	auto[FlashOpErase]	32	1		T131	2		T150	2		T114	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T150	4		T153	2		T391	2