Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33565	1		T5	28		T16	32		T62	20
auto[1]	28	1		T392	1		T280	2		T125	1
auto[2]	38	1		T160	4		T224	2		T134	1
auto[3]	254	1		T21	1		T393	1		T149	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8474	1		T5	7		T16	8		T62	5
evic_idx[1]	8466	1		T5	7		T16	8		T62	5
evic_idx[2]	8475	1		T5	7		T16	8		T62	5
evic_idx[3]	8470	1		T5	7		T16	8		T62	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32939	1		T16	16		T36	440		T199	4
evic_op[2]	322	1		T16	16		T75	28		T199	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8174	1		T16	4		T36	110		T199	1
evic_idx[0]	evic_op[1]	auto[1]	5	1		T394	2		T395	3		-	-
evic_idx[0]	evic_op[1]	auto[2]	2	1		T396	1		T394	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	58	1		T134	1		T397	6		T398	2
evic_idx[0]	evic_op[2]	auto[0]	69	1		T16	4		T75	7		T199	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T399	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T224	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	8	1		T224	1		T400	1		T401	1
evic_idx[1]	evic_op[1]	auto[0]	8174	1		T16	4		T36	110		T199	1
evic_idx[1]	evic_op[1]	auto[1]	3	1		T402	1		T394	1		T395	1
evic_idx[1]	evic_op[1]	auto[2]	2	1		T396	1		T394	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	57	1		T134	1		T397	5		T398	2
evic_idx[1]	evic_op[2]	auto[0]	64	1		T16	4		T75	7		T199	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T280	1		T399	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	1	1		T403	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	7	1		T404	1		T405	1		T406	1
evic_idx[2]	evic_op[1]	auto[0]	8173	1		T16	4		T36	110		T199	1
evic_idx[2]	evic_op[1]	auto[1]	3	1		T402	1		T394	1		T395	1
evic_idx[2]	evic_op[1]	auto[2]	2	1		T134	1		T394	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	55	1		T397	5		T398	2		T407	3
evic_idx[2]	evic_op[2]	auto[0]	69	1		T16	4		T75	7		T199	1
evic_idx[2]	evic_op[2]	auto[1]	6	1		T280	1		T125	1		T408	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T406	1		T409	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	9	1		T393	1		T149	1		T410	1
evic_idx[3]	evic_op[1]	auto[0]	8174	1		T16	4		T36	110		T199	1
evic_idx[3]	evic_op[1]	auto[1]	4	1		T402	2		T394	1		T395	1
evic_idx[3]	evic_op[1]	auto[2]	1	1		T394	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	52	1		T397	6		T398	2		T407	1
evic_idx[3]	evic_op[2]	auto[0]	68	1		T16	4		T75	7		T199	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T392	1		T411	1		T412	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T224	1		T413	1		T414	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T21	1		T415	1		T416	1