Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
3597 | 
1 | 
 | 
T42 | 
100 | 
 | 
T43 | 
48 | 
 | 
T44 | 
86 | 
| instr_types[0] | 
4616 | 
1 | 
 | 
T42 | 
171 | 
 | 
T43 | 
188 | 
 | 
T44 | 
172 | 
| instr_types[1] | 
4167007 | 
1 | 
 | 
T1 | 
164 | 
 | 
T3 | 
16711 | 
 | 
T6 | 
16799 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4173772 | 
1 | 
 | 
T1 | 
164 | 
 | 
T3 | 
16711 | 
 | 
T6 | 
16799 | 
| auto[1] | 
1448 | 
1 | 
 | 
T42 | 
165 | 
 | 
T43 | 
109 | 
 | 
T44 | 
119 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
3270 | 
1 | 
 | 
T42 | 
77 | 
 | 
T43 | 
24 | 
 | 
T44 | 
58 | 
| auto[0] | 
instr_types[0] | 
4040 | 
1 | 
 | 
T42 | 
118 | 
 | 
T43 | 
141 | 
 | 
T44 | 
114 | 
| auto[0] | 
instr_types[1] | 
4166462 | 
1 | 
 | 
T1 | 
164 | 
 | 
T3 | 
16711 | 
 | 
T6 | 
16799 | 
| auto[1] | 
others | 
327 | 
1 | 
 | 
T42 | 
23 | 
 | 
T43 | 
24 | 
 | 
T44 | 
28 | 
| auto[1] | 
instr_types[0] | 
576 | 
1 | 
 | 
T42 | 
53 | 
 | 
T43 | 
47 | 
 | 
T44 | 
58 | 
| auto[1] | 
instr_types[1] | 
545 | 
1 | 
 | 
T42 | 
89 | 
 | 
T43 | 
38 | 
 | 
T44 | 
33 |