Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	38843	1		T50	15283		T40	2688		T319	14813
rd_lvl[2]	47596	1		T50	11053		T40	2353		T319	10899
rd_lvl[3]	15213	1		T40	1436		T320	569		T321	1291
rd_lvl[4]	45877	1		T51	5583		T40	1615		T320	529
rd_lvl[5]	14631	1		T51	1179		T40	1466		T217	2464
rd_lvl[6]	13918	1		T6	699		T40	1		T217	2690
rd_lvl[7]	9382	1		T6	247		T40	1436		T136	448
rd_lvl[8]	21244	1		T40	1435		T136	1482		T320	185
rd_lvl[9]	7918	1		T6	5		T40	1840		T136	1230
rd_lvl[10]	4112	1		T6	4		T40	1030		T216	758
rd_lvl[11]	2412	1		T216	232		T320	131		T322	1
rd_lvl[12]	6092	1		T27	57		T323	246		T322	121
rd_lvl[13]	4805	1		T27	9		T324	787		T325	170
rd_lvl[14]	13102	1		T3	167		T324	866		T325	1445
rd_lvl[15]	4113	1		T3	1479		T19	411		T27	1