Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	366082	1		T1	2		T2	1		T3	3293
all_pins[1]	366082	1		T1	2		T2	1		T3	3293
all_pins[2]	366082	1		T1	2		T2	1		T3	3293
all_pins[3]	366082	1		T1	2		T2	1		T3	3293
all_pins[4]	366082	1		T1	2		T2	1		T3	3293
all_pins[5]	366082	1		T1	2		T2	1		T3	3293

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1824909	1		T1	12		T2	6		T3	16466
values[0x1]	371583	1		T3	3292		T6	1506		T19	4100
transitions[0x0=>0x1]	330679	1		T3	3292		T6	1502		T19	2440
transitions[0x1=>0x0]	330661	1		T3	3292		T6	1502		T19	2440

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	365907	1		T1	2		T2	1		T3	3293
all_pins[0]	values[0x1]	175	1		T264	1		T265	1		T266	3
all_pins[0]	transitions[0x0=>0x1]	87	1		T312	3		T313	4		T315	1
all_pins[0]	transitions[0x1=>0x0]	86	1		T264	3		T265	3		T266	2
all_pins[1]	values[0x0]	365908	1		T1	2		T2	1		T3	3293
all_pins[1]	values[0x1]	174	1		T264	4		T265	4		T266	5
all_pins[1]	transitions[0x0=>0x1]	143	1		T264	3		T265	3		T266	3
all_pins[1]	transitions[0x1=>0x0]	2463	1		T19	830		T330	11		T331	1592
all_pins[2]	values[0x0]	363588	1		T1	2		T2	1		T3	3293
all_pins[2]	values[0x1]	2494	1		T19	830		T330	11		T331	1592
all_pins[2]	transitions[0x0=>0x1]	44	1		T264	1		T266	2		T312	1
all_pins[2]	transitions[0x1=>0x0]	249508	1		T3	1646		T6	955		T19	411
all_pins[3]	values[0x0]	114124	1		T1	2		T2	1		T3	1647
all_pins[3]	values[0x1]	251958	1		T3	1646		T6	955		T19	1241
all_pins[3]	transitions[0x0=>0x1]	213677	1		T3	1646		T6	951		T19	411
all_pins[3]	transitions[0x1=>0x0]	78440	1		T3	1646		T6	547		T19	1199
all_pins[4]	values[0x0]	249361	1		T1	2		T2	1		T3	1647
all_pins[4]	values[0x1]	116721	1		T3	1646		T6	551		T19	2029
all_pins[4]	transitions[0x0=>0x1]	116707	1		T3	1646		T6	551		T19	2029
all_pins[4]	transitions[0x1=>0x0]	47	1		T312	1		T313	1		T314	2
all_pins[5]	values[0x0]	366021	1		T1	2		T2	1		T3	3293
all_pins[5]	values[0x1]	61	1		T312	1		T313	3		T314	2
all_pins[5]	transitions[0x0=>0x1]	21	1		T314	1		T315	1		T316	3
all_pins[5]	transitions[0x1=>0x0]	117	1		T264	1		T265	1		T266	2