Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	293	1		T264	4		T265	4		T266	4
all_values[1]	293	1		T264	4		T265	4		T266	4
all_values[2]	293	1		T264	4		T265	4		T266	4
all_values[3]	293	1		T264	4		T265	4		T266	4
all_values[4]	293	1		T264	4		T265	4		T266	4
all_values[5]	293	1		T264	4		T265	4		T266	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	976	1		T264	18		T265	15		T266	15
auto[1]	782	1		T264	6		T265	9		T266	9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	552	1		T264	7		T265	8		T266	6
auto[1]	1206	1		T264	17		T265	16		T266	18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1029	1		T264	14		T265	12		T266	13
auto[1]	729	1		T264	10		T265	12		T266	11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	96	1		T264	3		T265	2		T266	2
all_values[0]	auto[0]	auto[1]	auto[1]	79	1		T266	1		T312	3		T313	2
all_values[0]	auto[1]	auto[0]	auto[1]	73	1		T264	1		T265	1		T266	1
all_values[0]	auto[1]	auto[1]	auto[1]	45	1		T265	1		T312	2		T313	1
all_values[1]	auto[0]	auto[0]	auto[1]	88	1		T264	2		T312	2		T313	2
all_values[1]	auto[0]	auto[1]	auto[1]	93	1		T264	1		T265	1		T266	2
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T264	1		T265	1		T266	1
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T265	2		T266	1		T312	3
all_values[2]	auto[0]	auto[0]	auto[0]	75	1		T264	1		T265	1		T266	1
all_values[2]	auto[0]	auto[1]	auto[0]	88	1		T264	1		T265	1		T266	1
all_values[2]	auto[1]	auto[0]	auto[1]	75	1		T264	2		T265	1		T312	1
all_values[2]	auto[1]	auto[1]	auto[1]	55	1		T265	1		T266	2		T312	3
all_values[3]	auto[0]	auto[0]	auto[0]	104	1		T264	2		T265	1		T266	2
all_values[3]	auto[0]	auto[1]	auto[0]	57	1		T265	1		T312	3		T314	2
all_values[3]	auto[1]	auto[0]	auto[1]	77	1		T265	1		T266	2		T312	2
all_values[3]	auto[1]	auto[1]	auto[1]	55	1		T264	2		T265	1		T312	1
all_values[4]	auto[0]	auto[0]	auto[0]	58	1		T264	2		T265	1		T312	1
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T265	1		T266	1		T312	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T315	2		T316	1		T317	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T313	1		T316	1		T318	4
all_values[4]	auto[1]	auto[0]	auto[1]	70	1		T265	1		T266	1		T312	1
all_values[4]	auto[1]	auto[1]	auto[1]	63	1		T264	2		T265	1		T266	2
all_values[5]	auto[0]	auto[0]	auto[0]	70	1		T264	1		T265	3		T266	2
all_values[5]	auto[0]	auto[0]	auto[1]	32	1		T264	1		T266	1		T313	1
all_values[5]	auto[0]	auto[1]	auto[0]	57	1		T312	2		T315	1		T316	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T313	1		T314	2		T316	3
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T264	2		T265	1		T266	1
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T312	2		T313	1		T315	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal