Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	412922	1		T1	6652		T2	2		T3	1
all_values[1]	412922	1		T1	6652		T2	2		T3	1
all_values[2]	412922	1		T1	6652		T2	2		T3	1
all_values[3]	412922	1		T1	6652		T2	2		T3	1
all_values[4]	412922	1		T1	6652		T2	2		T3	1
all_values[5]	412922	1		T1	6652		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	832243	1		T1	13308		T2	12		T3	6
auto[1]	1645289	1		T1	26604		T27	6464		T38	13344

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1213544	1		T1	18294		T2	7		T3	4
auto[1]	1263988	1		T1	21618		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	412758	1		T1	6652		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	164	1		T272	7		T335	5		T336	4
all_values[1]	auto[0]	auto[1]	412762	1		T1	6652		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	160	1		T271	2		T272	2		T335	2
all_values[2]	auto[0]	auto[0]	1642	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	58	1		T271	2		T335	2		T338	1
all_values[2]	auto[1]	auto[0]	411180	1		T1	6651		T27	1616		T38	3336
all_values[2]	auto[1]	auto[1]	42	1		T272	2		T335	1		T336	1
all_values[3]	auto[0]	auto[0]	1599	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	48	1		T272	1		T335	1		T339	1
all_values[3]	auto[1]	auto[0]	80549	1		T27	1616		T38	1668		T30	1587
all_values[3]	auto[1]	auto[1]	330726	1		T1	6651		T38	1668		T32	365
all_values[4]	auto[0]	auto[0]	1145	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	545	1		T2	1		T19	1		T4	1
all_values[4]	auto[1]	auto[0]	304657	1		T1	4988		T27	1		T38	1668
all_values[4]	auto[1]	auto[1]	106575	1		T1	1663		T27	1615		T38	1668
all_values[5]	auto[0]	auto[0]	1591	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	95	1		T5	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	411181	1		T1	6651		T27	1616		T38	3336
all_values[5]	auto[1]	auto[1]	55	1		T272	1		T335	4		T336	2