Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	241570	1		T1	914		T2	36		T3	1480
auto[FlashEraseBank]	271376	1		T1	749		T2	34		T4	2

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256619	1		T1	1663		T3	738		T19	20
auto[FlashOpProgram]	236608	1		T2	70		T3	371		T17	1
auto[FlashOpErase]	15719	1		T3	371		T4	5		T42	3
auto[FlashOpInvalid]	4000	1		T88	200		T89	200		T218	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256619	1		T1	1663		T3	738		T19	20
op[FlashOpProgram]	236608	1		T2	70		T3	371		T17	1
op[FlashOpErase]	15719	1		T3	371		T4	5		T42	3
read_erase_read	558	1		T42	2		T29	16		T34	1
read_prog_read	776	1		T42	2		T5	3		T25	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	367864	1		T1	1663		T2	70		T17	1
auto[FlashPartInfo]	141663	1		T3	1480		T4	3		T42	3
auto[FlashPartInfo1]	785	1		T42	6		T45	3		T57	2
auto[FlashPartInfo2]	2634	1		T5	5		T45	11		T27	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183344	1		T1	1663		T19	20		T4	6
auto[FlashPartData]	auto[FlashOpProgram]	177022	1		T2	70		T17	1		T4	6
auto[FlashPartData]	auto[FlashOpErase]	3604	1		T4	4		T42	2		T43	1
auto[FlashPartData]	auto[FlashOpInvalid]	3894	1		T88	190		T89	196		T218	198
auto[FlashPartInfo]	auto[FlashOpRead]	70965	1		T3	738		T4	1		T42	1
auto[FlashPartInfo]	auto[FlashOpProgram]	58519	1		T3	371		T4	1		T42	1
auto[FlashPartInfo]	auto[FlashOpErase]	12089	1		T3	371		T4	1		T42	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	90	1		T88	10		T89	4		T218	2
auto[FlashPartInfo1]	auto[FlashOpRead]	619	1		T42	6		T45	3		T57	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T128	32		T129	1		T146	1
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T129	1		-	-		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T129	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1691	1		T5	4		T45	4		T57	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	904	1		T5	1		T45	7		T27	7
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T158	1		T161	1		T162	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T158	2		T162	4		T426	2