Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30866	1		T3	720		T4	1		T47	280
auto[1]	44	1		T140	1		T217	4		T91	2
auto[2]	100	1		T356	5		T159	4		T357	20
auto[3]	232	1		T29	16		T28	1		T41	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7814	1		T3	180		T47	70		T29	6
evic_idx[1]	7812	1		T3	180		T47	70		T29	4
evic_idx[2]	7808	1		T3	180		T4	1		T47	70
evic_idx[3]	7808	1		T3	180		T47	70		T29	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30400	1		T3	720		T47	280		T29	16
evic_op[2]	266	1		T4	1		T28	1		T41	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7523	1		T3	180		T47	70		T103	30
evic_idx[0]	evic_op[1]	auto[1]	9	1		T358	2		T359	1		T360	3
evic_idx[0]	evic_op[1]	auto[2]	18	1		T356	2		T357	4		T361	2
evic_idx[0]	evic_op[1]	auto[3]	53	1		T29	6		T217	2		T362	6
evic_idx[0]	evic_op[2]	auto[0]	53	1		T35	1		T363	1		T216	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T140	1		T364	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	5	1		T159	2		T365	2		T366	1
evic_idx[0]	evic_op[2]	auto[3]	7	1		T214	1		T318	1		T367	1
evic_idx[1]	evic_op[1]	auto[0]	7524	1		T3	180		T47	70		T103	30
evic_idx[1]	evic_op[1]	auto[1]	8	1		T217	1		T358	2		T359	1
evic_idx[1]	evic_op[1]	auto[2]	20	1		T357	8		T361	1		T368	4
evic_idx[1]	evic_op[1]	auto[3]	55	1		T29	4		T217	1		T362	7
evic_idx[1]	evic_op[2]	auto[0]	55	1		T143	1		T35	1		T363	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T159	1		T369	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	4	1		T370	1		T371	1		T372	1
evic_idx[2]	evic_op[1]	auto[0]	7523	1		T3	180		T47	70		T103	30
evic_idx[2]	evic_op[1]	auto[1]	8	1		T358	3		T359	1		T360	1
evic_idx[2]	evic_op[1]	auto[2]	16	1		T356	2		T357	5		T361	1
evic_idx[2]	evic_op[1]	auto[3]	49	1		T29	3		T362	6		T358	1
evic_idx[2]	evic_op[2]	auto[0]	53	1		T4	1		T35	1		T363	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T91	1		T373	1		T374	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T159	1		T369	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T28	1		T41	1		T134	1
evic_idx[3]	evic_op[1]	auto[0]	7522	1		T3	180		T47	70		T103	30
evic_idx[3]	evic_op[1]	auto[1]	9	1		T217	3		T358	2		T359	1
evic_idx[3]	evic_op[1]	auto[2]	17	1		T356	1		T357	3		T361	1
evic_idx[3]	evic_op[1]	auto[3]	46	1		T29	3		T217	1		T362	7
evic_idx[3]	evic_op[2]	auto[0]	53	1		T35	1		T363	1		T375	4
evic_idx[3]	evic_op[2]	auto[1]	5	1		T91	1		T376	1		T377	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T378	1		T365	1		T369	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T155	1		T205	1		T379	1