Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5575 | 
1 | 
 | 
T23 | 
114 | 
 | 
T52 | 
88 | 
 | 
T53 | 
228 | 
| instr_types[0] | 
6556 | 
1 | 
 | 
T23 | 
122 | 
 | 
T52 | 
222 | 
 | 
T53 | 
284 | 
| instr_types[1] | 
4131394 | 
1 | 
 | 
T1 | 
16958 | 
 | 
T4 | 
235 | 
 | 
T22 | 
10 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4141559 | 
1 | 
 | 
T1 | 
16958 | 
 | 
T4 | 
235 | 
 | 
T22 | 
10 | 
| auto[1] | 
1966 | 
1 | 
 | 
T23 | 
132 | 
 | 
T52 | 
225 | 
 | 
T53 | 
249 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
5127 | 
1 | 
 | 
T23 | 
90 | 
 | 
T52 | 
74 | 
 | 
T53 | 
175 | 
| auto[0] | 
instr_types[0] | 
5722 | 
1 | 
 | 
T23 | 
84 | 
 | 
T52 | 
117 | 
 | 
T53 | 
180 | 
| auto[0] | 
instr_types[1] | 
4130710 | 
1 | 
 | 
T1 | 
16958 | 
 | 
T4 | 
235 | 
 | 
T22 | 
10 | 
| auto[1] | 
others | 
448 | 
1 | 
 | 
T23 | 
24 | 
 | 
T52 | 
14 | 
 | 
T53 | 
53 | 
| auto[1] | 
instr_types[0] | 
834 | 
1 | 
 | 
T23 | 
38 | 
 | 
T52 | 
105 | 
 | 
T53 | 
104 | 
| auto[1] | 
instr_types[1] | 
684 | 
1 | 
 | 
T23 | 
70 | 
 | 
T52 | 
106 | 
 | 
T53 | 
92 |