Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	62370	1		T167	15973		T99	16408		T341	14130
rd_lvl[2]	73607	1		T167	11867		T342	11652		T99	12295
rd_lvl[3]	14542	1		T343	711		T342	510		T98	4006
rd_lvl[4]	34774	1		T1	5592		T343	2130		T344	5352
rd_lvl[5]	13417	1		T1	1058		T343	110		T344	840
rd_lvl[6]	12140	1		T345	122		T343	1422		T346	331
rd_lvl[7]	6113	1		T345	37		T343	1419		T347	396
rd_lvl[8]	13163	1		T1	1		T343	1418		T348	2844
rd_lvl[9]	7279	1		T209	212		T345	1		T348	272
rd_lvl[10]	9811	1		T38	1341		T209	174		T349	1609
rd_lvl[11]	2504	1		T38	327		T36	161		T350	271
rd_lvl[12]	4902	1		T36	61		T351	1342		T352	385
rd_lvl[13]	3159	1		T353	487		T351	243		T352	202
rd_lvl[14]	7739	1		T36	28		T37	1443		T353	1187
rd_lvl[15]	2194	1		T32	224		T37	409		T354	381