Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	412922	1		T1	6652		T2	2		T3	1
all_pins[1]	412922	1		T1	6652		T2	2		T3	1
all_pins[2]	412922	1		T1	6652		T2	2		T3	1
all_pins[3]	412922	1		T1	6652		T2	2		T3	1
all_pins[4]	412922	1		T1	6652		T2	2		T3	1
all_pins[5]	412922	1		T1	6652		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2085159	1		T1	31598		T2	12		T3	6
values[0x1]	392373	1		T1	8314		T27	1615		T38	3336
transitions[0x0=>0x1]	351395	1		T1	6651		T27	1615		T38	3336
transitions[0x1=>0x0]	351375	1		T1	6651		T27	1615		T38	3336

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	412758	1		T1	6652		T2	2		T3	1
all_pins[0]	values[0x1]	164	1		T272	7		T335	5		T336	4
all_pins[0]	transitions[0x0=>0x1]	93	1		T272	6		T335	5		T336	1
all_pins[0]	transitions[0x1=>0x0]	89	1		T271	2		T272	1		T335	2
all_pins[1]	values[0x0]	412762	1		T1	6652		T2	2		T3	1
all_pins[1]	values[0x1]	160	1		T271	2		T272	2		T335	2
all_pins[1]	transitions[0x0=>0x1]	135	1		T271	2		T272	1		T335	2
all_pins[1]	transitions[0x1=>0x0]	2628	1		T32	141		T354	201		T380	1414
all_pins[2]	values[0x0]	410269	1		T1	6652		T2	2		T3	1
all_pins[2]	values[0x1]	2653	1		T32	141		T354	201		T380	1414
all_pins[2]	transitions[0x0=>0x1]	32	1		T272	2		T336	1		T337	1
all_pins[2]	transitions[0x1=>0x0]	267851	1		T1	6651		T38	1668		T32	224
all_pins[3]	values[0x0]	142450	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	270472	1		T1	6651		T38	1668		T32	365
all_pins[3]	transitions[0x0=>0x1]	232260	1		T1	4988		T38	1668		T32	224
all_pins[3]	transitions[0x1=>0x0]	80657	1		T27	1615		T38	1668		T30	1586
all_pins[4]	values[0x0]	294053	1		T1	4989		T2	2		T3	1
all_pins[4]	values[0x1]	118869	1		T1	1663		T27	1615		T38	1668
all_pins[4]	transitions[0x0=>0x1]	118853	1		T1	1663		T27	1615		T38	1668
all_pins[4]	transitions[0x1=>0x0]	39	1		T272	1		T335	2		T336	2
all_pins[5]	values[0x0]	412867	1		T1	6652		T2	2		T3	1
all_pins[5]	values[0x1]	55	1		T272	1		T335	4		T336	2
all_pins[5]	transitions[0x0=>0x1]	22	1		T335	2		T336	1		T340	2
all_pins[5]	transitions[0x1=>0x0]	111	1		T272	5		T335	2		T336	2