Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T271	4		T272	7		T335	7
all_values[1]	284	1		T271	4		T272	7		T335	7
all_values[2]	284	1		T271	4		T272	7		T335	7
all_values[3]	284	1		T271	4		T272	7		T335	7
all_values[4]	284	1		T271	4		T272	7		T335	7
all_values[5]	284	1		T271	4		T272	7		T335	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	949	1		T271	11		T272	22		T335	23
auto[1]	755	1		T271	13		T272	20		T335	19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	576	1		T271	10		T272	15		T335	9
auto[1]	1128	1		T271	14		T272	27		T335	33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1022	1		T271	18		T272	26		T335	20
auto[1]	682	1		T271	6		T272	16		T335	22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	87	1		T271	4		T272	1		T335	1
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T272	4		T335	1		T336	1
all_values[0]	auto[1]	auto[0]	auto[1]	80	1		T272	1		T335	3		T336	2
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T272	1		T335	2		T336	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1		T271	1		T272	2		T335	3
all_values[1]	auto[0]	auto[1]	auto[1]	75	1		T271	2		T335	1		T336	2
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T272	2		T335	2		T336	1
all_values[1]	auto[1]	auto[1]	auto[1]	51	1		T271	1		T272	3		T335	1
all_values[2]	auto[0]	auto[0]	auto[0]	107	1		T271	1		T272	3		T335	3
all_values[2]	auto[0]	auto[1]	auto[0]	77	1		T271	1		T272	2		T335	1
all_values[2]	auto[1]	auto[0]	auto[1]	61	1		T271	1		T272	1		T335	1
all_values[2]	auto[1]	auto[1]	auto[1]	39	1		T271	1		T272	1		T335	2
all_values[3]	auto[0]	auto[0]	auto[0]	69	1		T272	2		T335	1		T336	2
all_values[3]	auto[0]	auto[1]	auto[0]	98	1		T271	3		T272	4		T335	2
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T272	1		T335	2		T336	1
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T271	1		T335	2		T336	1
all_values[4]	auto[0]	auto[0]	auto[0]	61	1		T271	2		T272	1		T335	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T272	1		T335	3		T337	1
all_values[4]	auto[0]	auto[1]	auto[0]	44	1		T271	1		T272	1		T338	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T272	1		T335	1		T338	1
all_values[4]	auto[1]	auto[0]	auto[1]	73	1		T272	2		T335	1		T336	2
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T271	1		T272	1		T335	1
all_values[5]	auto[0]	auto[0]	auto[0]	65	1		T272	1		T335	1		T338	1
all_values[5]	auto[0]	auto[0]	auto[1]	35	1		T271	1		T272	2		T339	2
all_values[5]	auto[0]	auto[1]	auto[0]	55	1		T271	2		T272	1		T336	1
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T335	1		T336	1		T340	1
all_values[5]	auto[1]	auto[0]	auto[1]	58	1		T271	1		T272	2		T335	1
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T272	1		T335	4		T336	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal