Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_intr
Bins
| | | | | | | | | | | |
all_values[0] |
281021 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[1] |
281021 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[2] |
281021 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[3] |
281021 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[4] |
281021 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[5] |
281021 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | |
auto[0] |
568254 |
1 |
|
T1 |
12 |
|
T3 |
12 |
|
T4 |
12 |
auto[1] |
1117872 |
1 |
|
T21 |
6248 |
|
T6 |
13440 |
|
T7 |
13912 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | |
auto[0] |
820081 |
1 |
|
T1 |
7 |
|
T3 |
7 |
|
T4 |
7 |
auto[1] |
866045 |
1 |
|
T1 |
5 |
|
T3 |
5 |
|
T4 |
5 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
24 |
4 |
20 |
83.33 |
4 |
Automatically Generated Cross Bins for intr_cg_cc
Element holes
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
[all_values[0] , all_values[1]] |
* |
[auto[0]] |
-- |
-- |
4 |
Covered bins
| | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[1] |
280883 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[0] |
auto[1] |
auto[1] |
138 |
1 |
|
T260 |
1 |
|
T261 |
4 |
|
T321 |
3 |
all_values[1] |
auto[0] |
auto[1] |
280887 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[1] |
auto[1] |
auto[1] |
134 |
1 |
|
T260 |
1 |
|
T261 |
4 |
|
T322 |
2 |
all_values[2] |
auto[0] |
auto[0] |
1567 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[2] |
auto[0] |
auto[1] |
60 |
1 |
|
T260 |
2 |
|
T261 |
1 |
|
T321 |
1 |
all_values[2] |
auto[1] |
auto[0] |
279341 |
1 |
|
T21 |
1562 |
|
T6 |
3360 |
|
T7 |
3478 |
all_values[2] |
auto[1] |
auto[1] |
53 |
1 |
|
T260 |
2 |
|
T261 |
1 |
|
T321 |
1 |
all_values[3] |
auto[0] |
auto[0] |
1560 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[3] |
auto[0] |
auto[1] |
57 |
1 |
|
T260 |
3 |
|
T261 |
1 |
|
T322 |
1 |
all_values[3] |
auto[1] |
auto[0] |
84900 |
1 |
|
T21 |
1562 |
|
T6 |
1680 |
|
T7 |
1739 |
all_values[3] |
auto[1] |
auto[1] |
194504 |
1 |
|
T6 |
1680 |
|
T7 |
1739 |
|
T39 |
3372 |
all_values[4] |
auto[0] |
auto[0] |
1114 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
all_values[4] |
auto[0] |
auto[1] |
512 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
all_values[4] |
auto[1] |
auto[0] |
170721 |
1 |
|
T21 |
1 |
|
T6 |
1680 |
|
T7 |
1739 |
all_values[4] |
auto[1] |
auto[1] |
108674 |
1 |
|
T21 |
1561 |
|
T6 |
1680 |
|
T7 |
1739 |
all_values[5] |
auto[0] |
auto[0] |
1533 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
all_values[5] |
auto[0] |
auto[1] |
81 |
1 |
|
T8 |
1 |
|
T40 |
1 |
|
T41 |
1 |
all_values[5] |
auto[1] |
auto[0] |
279345 |
1 |
|
T21 |
1562 |
|
T6 |
3360 |
|
T7 |
3478 |
all_values[5] |
auto[1] |
auto[1] |
62 |
1 |
|
T260 |
2 |
|
T261 |
3 |
|
T322 |
1 |