Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	240180	1		T1	47		T3	185		T4	777
auto[FlashEraseBank]	268059	1		T1	34		T4	706		T21	779

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259989	1		T3	14		T5	8		T6	1680
auto[FlashOpProgram]	229460	1		T1	81		T3	160		T4	1483
auto[FlashOpErase]	14790	1		T3	11		T5	13		T22	8
auto[FlashOpInvalid]	4000	1		T48	200		T140	200		T144	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259989	1		T3	14		T5	8		T6	1680
op[FlashOpProgram]	229460	1		T1	81		T3	160		T4	1483
op[FlashOpErase]	14790	1		T3	11		T5	13		T22	8
read_erase_read	581	1		T3	1		T22	3		T35	2
read_prog_read	846	1		T22	11		T23	1		T28	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	372940	1		T1	81		T4	1265		T21	1315
auto[FlashPartInfo]	131251	1		T3	185		T4	212		T5	309
auto[FlashPartInfo1]	1018	1		T22	12		T44	1		T56	1
auto[FlashPartInfo2]	3030	1		T4	6		T21	5		T22	11

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	193394	1		T6	1680		T7	1739		T22	27
auto[FlashPartData]	auto[FlashOpProgram]	172036	1		T1	81		T4	1265		T21	1315
auto[FlashPartData]	auto[FlashOpErase]	3594	1		T22	4		T14	6		T71	27
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T48	194		T140	196		T144	192
auto[FlashPartInfo]	auto[FlashOpRead]	63697	1		T3	14		T5	8		T22	14
auto[FlashPartInfo]	auto[FlashOpProgram]	56323	1		T3	160		T4	212		T5	288
auto[FlashPartInfo]	auto[FlashOpErase]	11163	1		T3	11		T5	13		T22	3
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T48	4		T140	4		T144	6
auto[FlashPartInfo1]	auto[FlashOpRead]	843	1		T22	12		T44	1		T56	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T48	1		T127	1		T128	32
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T48	1		T130	1		T149	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T48	2		T396	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2055	1		T22	4		T28	1		T8	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	935	1		T4	6		T21	5		T22	6
auto[FlashPartInfo2]	auto[FlashOpErase]	28	1		T22	1		T29	1		T144	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T144	2		T397	4		T398	2