Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29205	1		T22	4		T47	88		T71	24
auto[1]	75	1		T32	2		T399	20		T400	17
auto[2]	68	1		T28	1		T67	4		T158	4
auto[3]	203	1		T28	1		T29	6		T32	13

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7395	1		T22	1		T28	1		T47	22
evic_idx[1]	7382	1		T22	1		T28	1		T47	22
evic_idx[2]	7387	1		T22	1		T47	22		T71	6
evic_idx[3]	7387	1		T22	1		T47	22		T71	6

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28528	1		T47	88		T83	316		T97	772
evic_op[2]	321	1		T28	2		T140	2		T401	36

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7066	1		T47	22		T83	79		T97	193
evic_idx[0]	evic_op[1]	auto[1]	17	1		T399	6		T400	4		T402	1
evic_idx[0]	evic_op[1]	auto[2]	7	1		T403	1		T399	1		T402	2
evic_idx[0]	evic_op[1]	auto[3]	51	1		T29	3		T32	4		T142	1
evic_idx[0]	evic_op[2]	auto[0]	64	1		T401	9		T385	1		T387	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T404	1		T85	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	5	1		T405	2		T406	1		T407	1
evic_idx[0]	evic_op[2]	auto[3]	7	1		T28	1		T408	1		T409	1
evic_idx[1]	evic_op[1]	auto[0]	7069	1		T47	22		T83	79		T97	193
evic_idx[1]	evic_op[1]	auto[1]	16	1		T399	3		T400	5		T402	1
evic_idx[1]	evic_op[1]	auto[2]	8	1		T403	1		T402	2		T410	2
evic_idx[1]	evic_op[1]	auto[3]	36	1		T29	1		T32	3		T142	2
evic_idx[1]	evic_op[2]	auto[0]	61	1		T401	9		T385	1		T233	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T85	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T28	1		T408	1		T395	1
evic_idx[1]	evic_op[2]	auto[3]	12	1		T411	1		T412	1		T413	1
evic_idx[2]	evic_op[1]	auto[0]	7067	1		T47	22		T83	79		T97	193
evic_idx[2]	evic_op[1]	auto[1]	15	1		T32	1		T399	6		T400	4
evic_idx[2]	evic_op[1]	auto[2]	6	1		T403	1		T402	2		T414	2
evic_idx[2]	evic_op[1]	auto[3]	39	1		T29	1		T32	3		T142	1
evic_idx[2]	evic_op[2]	auto[0]	63	1		T140	1		T401	9		T385	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T85	1		T415	1		T416	1
evic_idx[2]	evic_op[2]	auto[2]	9	1		T412	1		T408	1		T405	3
evic_idx[2]	evic_op[2]	auto[3]	10	1		T417	1		T418	1		T419	1
evic_idx[3]	evic_op[1]	auto[0]	7065	1		T47	22		T83	79		T97	193
evic_idx[3]	evic_op[1]	auto[1]	17	1		T32	1		T399	5		T400	4
evic_idx[3]	evic_op[1]	auto[2]	10	1		T403	2		T399	1		T402	2
evic_idx[3]	evic_op[1]	auto[3]	39	1		T29	1		T32	3		T142	1
evic_idx[3]	evic_op[2]	auto[0]	64	1		T140	1		T401	9		T385	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T420	1		T415	1		T421	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T284	2		T406	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	9	1		T31	1		T42	1		T422	1