Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6885	1		T66	1154		T330	1050		T331	2204
rd_lvl[2]	15245	1		T66	2332		T213	1145		T330	278
rd_lvl[3]	11016	1		T66	659		T213	313		T332	1836
rd_lvl[4]	32971	1		T66	1866		T213	11		T123	3466
rd_lvl[5]	21170	1		T60	2423		T66	207		T213	42
rd_lvl[6]	28864	1		T60	2593		T66	1522		T310	578
rd_lvl[7]	3565	1		T66	19		T310	209		T123	20
rd_lvl[8]	14337	1		T39	2922		T59	2629		T66	416
rd_lvl[9]	6241	1		T6	513		T39	450		T59	413
rd_lvl[10]	11256	1		T6	1167		T7	1436		T66	1
rd_lvl[11]	10748	1		T7	303		T66	2878		T276	503
rd_lvl[12]	11510	1		T36	179		T213	38		T276	1251
rd_lvl[13]	3835	1		T36	98		T213	38		T333	577
rd_lvl[14]	2959	1		T333	1082		T331	26		T334	1043
rd_lvl[15]	1337	1		T36	54		T335	141		T336	575