Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	281021	1		T1	2		T3	2		T4	2
all_pins[1]	281021	1		T1	2		T3	2		T4	2
all_pins[2]	281021	1		T1	2		T3	2		T4	2
all_pins[3]	281021	1		T1	2		T3	2		T4	2
all_pins[4]	281021	1		T1	2		T3	2		T4	2
all_pins[5]	281021	1		T1	2		T3	2		T4	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1383468	1		T1	12		T3	12		T4	12
values[0x1]	302658	1		T21	1561		T6	3360		T7	3478
transitions[0x0=>0x1]	269682	1		T21	1561		T6	3360		T7	3478
transitions[0x1=>0x0]	269666	1		T21	1561		T6	3360		T7	3478

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280883	1		T1	2		T3	2		T4	2
all_pins[0]	values[0x1]	138	1		T260	1		T261	4		T321	3
all_pins[0]	transitions[0x0=>0x1]	78	1		T260	1		T321	3		T322	2
all_pins[0]	transitions[0x1=>0x0]	74	1		T260	1		T325	3		T324	6
all_pins[1]	values[0x0]	280887	1		T1	2		T3	2		T4	2
all_pins[1]	values[0x1]	134	1		T260	1		T261	4		T322	2
all_pins[1]	transitions[0x0=>0x1]	106	1		T260	1		T261	3		T322	2
all_pins[1]	transitions[0x1=>0x0]	2247	1		T336	1151		T340	1071		T260	2
all_pins[2]	values[0x0]	278746	1		T1	2		T3	2		T4	2
all_pins[2]	values[0x1]	2275	1		T336	1151		T340	1071		T260	2
all_pins[2]	transitions[0x0=>0x1]	40	1		T260	2		T261	1		T321	1
all_pins[2]	transitions[0x1=>0x0]	181983	1		T6	1680		T7	1739		T39	3372
all_pins[3]	values[0x0]	96803	1		T1	2		T3	2		T4	2
all_pins[3]	values[0x1]	184218	1		T6	1680		T7	1739		T39	3372
all_pins[3]	transitions[0x0=>0x1]	153622	1		T6	1680		T7	1739		T39	1686
all_pins[3]	transitions[0x1=>0x0]	85235	1		T21	1561		T6	1680		T7	1739
all_pins[4]	values[0x0]	165190	1		T1	2		T3	2		T4	2
all_pins[4]	values[0x1]	115831	1		T21	1561		T6	1680		T7	1739
all_pins[4]	transitions[0x0=>0x1]	115811	1		T21	1561		T6	1680		T7	1739
all_pins[4]	transitions[0x1=>0x0]	42	1		T260	2		T261	3		T322	1
all_pins[5]	values[0x0]	280959	1		T1	2		T3	2		T4	2
all_pins[5]	values[0x1]	62	1		T260	2		T261	3		T322	1
all_pins[5]	transitions[0x0=>0x1]	25	1		T260	2		T261	1		T325	2
all_pins[5]	transitions[0x1=>0x0]	85	1		T260	1		T261	1		T321	2