Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T260	7		T261	4		T321	4
all_values[1]	266	1		T260	7		T261	4		T321	4
all_values[2]	266	1		T260	7		T261	4		T321	4
all_values[3]	266	1		T260	7		T261	4		T321	4
all_values[4]	266	1		T260	7		T261	4		T321	4
all_values[5]	266	1		T260	7		T261	4		T321	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	858	1		T260	21		T261	15		T321	16
auto[1]	738	1		T260	21		T261	9		T321	8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	528	1		T260	14		T261	7		T321	11
auto[1]	1068	1		T260	28		T261	17		T321	13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	926	1		T260	23		T261	14		T321	18
auto[1]	670	1		T260	19		T261	10		T321	6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	83	1		T260	2		T261	1		T321	1
all_values[0]	auto[0]	auto[1]	auto[1]	75	1		T261	1		T321	3		T322	3
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T260	4		T261	1		T322	2
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T260	1		T261	1		T322	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1		T260	6		T261	1		T321	3
all_values[1]	auto[0]	auto[1]	auto[1]	68	1		T261	2		T323	2		T324	3
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T260	1		T261	1		T321	1
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T322	2		T323	1		T325	5
all_values[2]	auto[0]	auto[0]	auto[0]	82	1		T260	1		T261	2		T321	1
all_values[2]	auto[0]	auto[1]	auto[0]	71	1		T260	2		T321	1		T322	3
all_values[2]	auto[1]	auto[0]	auto[1]	64	1		T260	2		T261	1		T321	2
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T260	2		T261	1		T322	1
all_values[3]	auto[0]	auto[0]	auto[0]	76	1		T260	1		T261	3		T321	4
all_values[3]	auto[0]	auto[1]	auto[0]	76	1		T260	2		T322	2		T325	2
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T260	3		T261	1		T322	1
all_values[3]	auto[1]	auto[1]	auto[1]	50	1		T260	1		T322	4		T323	1
all_values[4]	auto[0]	auto[0]	auto[0]	70	1		T260	1		T261	1		T321	2
all_values[4]	auto[0]	auto[0]	auto[1]	19	1		T322	1		T324	1		T326	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T260	4		T321	1		T323	1
all_values[4]	auto[0]	auto[1]	auto[1]	23	1		T323	1		T325	1		T327	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T261	2		T321	1		T322	2
all_values[4]	auto[1]	auto[1]	auto[1]	56	1		T260	2		T261	1		T323	2
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T261	1		T322	3		T323	2
all_values[5]	auto[0]	auto[0]	auto[1]	19	1		T325	1		T324	1		T328	2
all_values[5]	auto[0]	auto[1]	auto[0]	55	1		T260	3		T321	2		T322	2
all_values[5]	auto[0]	auto[1]	auto[1]	27	1		T260	1		T261	2		T325	2
all_values[5]	auto[1]	auto[0]	auto[1]	54	1		T321	1		T325	2		T329	2
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T260	3		T261	1		T321	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal