Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	316718	1		T1	2		T2	1		T3	1
all_values[1]	316718	1		T1	2		T2	1		T3	1
all_values[2]	316718	1		T1	2		T2	1		T3	1
all_values[3]	316718	1		T1	2		T2	1		T3	1
all_values[4]	316718	1		T1	2		T2	1		T3	1
all_values[5]	316718	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	639766	1		T1	12		T2	6		T3	6
auto[1]	1260542	1		T36	7000		T37	11928		T33	4904

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	925405	1		T1	7		T2	4		T3	4
auto[1]	974903	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	316564	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	154	1		T263	5		T264	4		T317	1
all_values[1]	auto[0]	auto[1]	316557	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	161	1		T263	2		T264	1		T317	5
all_values[2]	auto[0]	auto[0]	1614	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	54	1		T263	1		T317	1		T319	1
all_values[2]	auto[1]	auto[0]	314983	1		T36	1750		T37	2982		T33	1226
all_values[2]	auto[1]	auto[1]	67	1		T263	2		T264	1		T317	1
all_values[3]	auto[0]	auto[0]	1607	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	52	1		T263	2		T264	2		T317	1
all_values[3]	auto[1]	auto[0]	87123	1		T36	580		T37	1491		T33	613
all_values[3]	auto[1]	auto[1]	227936	1		T36	1170		T37	1491		T33	613
all_values[4]	auto[0]	auto[0]	1127	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	528	1		T1	1		T4	1		T10	1
all_values[4]	auto[1]	auto[0]	202391	1		T36	1165		T37	1491		T33	613
all_values[4]	auto[1]	auto[1]	112672	1		T36	585		T37	1491		T33	613
all_values[5]	auto[0]	auto[0]	1569	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	94	1		T22	1		T38	1		T39	1
all_values[5]	auto[1]	auto[0]	314991	1		T36	1750		T37	2982		T33	1226
all_values[5]	auto[1]	auto[1]	64	1		T263	3		T320	1		T331	2