Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	247407	1		T1	8		T2	5		T3	929
auto[FlashEraseBank]	271492	1		T1	1		T2	8		T17	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	264758	1		T1	5		T2	11		T3	467
auto[FlashOpProgram]	233943	1		T1	3		T2	2		T3	231
auto[FlashOpErase]	16198	1		T1	1		T3	231		T10	5
auto[FlashOpInvalid]	4000	1		T78	200		T293	200		T294	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	264758	1		T1	5		T2	11		T3	467
op[FlashOpProgram]	233943	1		T1	3		T2	2		T3	231
op[FlashOpErase]	16198	1		T1	1		T3	231		T10	5
read_erase_read	534	1		T24	9		T26	12		T60	9
read_prog_read	755	1		T1	1		T2	2		T5	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	376334	1		T1	9		T2	3		T17	1
auto[FlashPartInfo]	139053	1		T2	10		T3	929		T10	291
auto[FlashPartInfo1]	835	1		T22	3		T47	1		T57	1
auto[FlashPartInfo2]	2677	1		T5	8		T24	9		T22	3

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	193960	1		T1	5		T2	3		T4	2
auto[FlashPartData]	auto[FlashOpProgram]	174808	1		T1	3		T17	1		T4	1
auto[FlashPartData]	auto[FlashOpErase]	3658	1		T1	1		T10	2		T24	7
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T78	194		T293	198		T294	200
auto[FlashPartInfo]	auto[FlashOpRead]	68422	1		T2	8		T3	467		T10	192
auto[FlashPartInfo]	auto[FlashOpProgram]	58047	1		T2	2		T3	231		T10	96
auto[FlashPartInfo]	auto[FlashOpErase]	12504	1		T3	231		T10	3		T11	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T78	6		T293	2		T124	2
auto[FlashPartInfo1]	auto[FlashOpRead]	666	1		T22	3		T47	1		T57	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T142	32		T121	1		T122	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T124	1		T369	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T124	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1710	1		T5	3		T24	5		T22	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	923	1		T5	5		T120	3		T58	8
auto[FlashPartInfo2]	auto[FlashOpErase]	34	1		T24	4		T60	1		T332	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T124	2		T424	2		T425	2