Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32022	1		T3	456		T55	456		T97	540
auto[1]	28	1		T60	4		T332	5		T214	1
auto[2]	21	1		T79	4		T333	1		T163	4
auto[3]	256	1		T24	7		T26	8		T60	5

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8090	1		T3	114		T55	114		T24	2
evic_idx[1]	8079	1		T3	114		T55	114		T26	3
evic_idx[2]	8076	1		T3	114		T55	114		T24	3
evic_idx[3]	8082	1		T3	114		T55	114		T24	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31351	1		T3	456		T55	456		T24	7
evic_op[2]	316	1		T25	1		T140	1		T145	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7780	1		T3	114		T55	114		T97	135
evic_idx[0]	evic_op[1]	auto[1]	1	1		T60	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	62	1		T24	2		T26	1		T60	2
evic_idx[0]	evic_op[2]	auto[0]	64	1		T145	1		T334	1		T206	1
evic_idx[0]	evic_op[2]	auto[1]	5	1		T335	1		T336	1		T337	2
evic_idx[0]	evic_op[2]	auto[2]	2	1		T79	1		T338	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	10	1		T79	1		T333	1		T339	1
evic_idx[1]	evic_op[1]	auto[0]	7777	1		T3	114		T55	114		T97	135
evic_idx[1]	evic_op[1]	auto[1]	3	1		T60	1		T332	2		-	-
evic_idx[1]	evic_op[1]	auto[3]	57	1		T26	3		T60	1		T143	1
evic_idx[1]	evic_op[2]	auto[0]	63	1		T206	1		T123	1		T340	1
evic_idx[1]	evic_op[2]	auto[1]	5	1		T341	1		T342	1		T335	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T333	1		T338	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	7	1		T334	1		T141	1		T343	1
evic_idx[2]	evic_op[1]	auto[0]	7781	1		T3	114		T55	114		T97	135
evic_idx[2]	evic_op[1]	auto[1]	2	1		T60	1		T332	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	50	1		T24	3		T26	3		T60	1
evic_idx[2]	evic_op[2]	auto[0]	63	1		T206	1		T344	2		T345	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T214	1		T335	1		T336	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T79	2		T346	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T25	1		T145	1		T347	1
evic_idx[3]	evic_op[1]	auto[0]	7781	1		T3	114		T55	114		T97	135
evic_idx[3]	evic_op[1]	auto[1]	4	1		T60	1		T332	2		T348	1
evic_idx[3]	evic_op[1]	auto[3]	53	1		T24	2		T26	1		T60	1
evic_idx[3]	evic_op[2]	auto[0]	65	1		T206	1		T223	1		T225	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T349	1		T336	1		T337	2
evic_idx[3]	evic_op[2]	auto[2]	2	1		T79	1		T350	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	9	1		T140	1		T351	1		T352	1