Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	21710	1		T134	961		T322	1381		T323	2021
rd_lvl[2]	28598	1		T134	223		T322	1483		T323	726
rd_lvl[3]	9647	1		T324	4506		T322	679		T323	243
rd_lvl[4]	42497	1		T324	4194		T325	1133		T322	850
rd_lvl[5]	10790	1		T325	393		T322	270		T326	745
rd_lvl[6]	17577	1		T36	773		T325	15		T322	480
rd_lvl[7]	11171	1		T36	240		T325	164		T322	126
rd_lvl[8]	19544	1		T325	31		T322	217		T323	237
rd_lvl[9]	6510	1		T36	4		T322	413		T323	300
rd_lvl[10]	8971	1		T36	5		T33	313		T34	175
rd_lvl[11]	6041	1		T33	250		T34	38		T35	145
rd_lvl[12]	11653	1		T33	1		T34	1		T327	1308
rd_lvl[13]	2627	1		T33	49		T34	67		T35	138
rd_lvl[14]	7143	1		T37	1195		T328	1391		T323	57
rd_lvl[15]	1834	1		T37	296		T329	150		T330	253