Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	316718	1		T1	2		T2	1		T3	1
all_pins[1]	316718	1		T1	2		T2	1		T3	1
all_pins[2]	316718	1		T1	2		T2	1		T3	1
all_pins[3]	316718	1		T1	2		T2	1		T3	1
all_pins[4]	316718	1		T1	2		T2	1		T3	1
all_pins[5]	316718	1		T1	2		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1569555	1		T1	12		T2	6		T3	6
values[0x1]	330753	1		T36	1607		T37	2982		T33	1226
transitions[0x0=>0x1]	296511	1		T36	1602		T37	2982		T33	1226
transitions[0x1=>0x0]	296490	1		T36	1602		T37	2982		T33	1226

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	316564	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	154	1		T263	5		T264	4		T317	1
all_pins[0]	transitions[0x0=>0x1]	78	1		T263	3		T264	3		T318	5
all_pins[0]	transitions[0x1=>0x0]	85	1		T317	4		T318	1		T319	1
all_pins[1]	values[0x0]	316557	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	161	1		T263	2		T264	1		T317	5
all_pins[1]	transitions[0x0=>0x1]	128	1		T263	2		T264	1		T317	4
all_pins[1]	transitions[0x1=>0x0]	2459	1		T329	1100		T356	181		T87	1144
all_pins[2]	values[0x0]	314226	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	2492	1		T329	1100		T356	181		T87	1144
all_pins[2]	transitions[0x0=>0x1]	52	1		T263	2		T264	1		T317	1
all_pins[2]	transitions[0x1=>0x0]	206630	1		T36	1022		T37	1491		T33	613
all_pins[3]	values[0x0]	107648	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	209070	1		T36	1022		T37	1491		T33	613
all_pins[3]	transitions[0x0=>0x1]	177425	1		T36	1017		T37	1491		T33	613
all_pins[3]	transitions[0x1=>0x0]	87167	1		T36	580		T37	1491		T33	613
all_pins[4]	values[0x0]	197906	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	118812	1		T36	585		T37	1491		T33	613
all_pins[4]	transitions[0x0=>0x1]	118793	1		T36	585		T37	1491		T33	613
all_pins[4]	transitions[0x1=>0x0]	45	1		T263	2		T331	2		T321	2
all_pins[5]	values[0x0]	316654	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	64	1		T263	3		T320	1		T331	2
all_pins[5]	transitions[0x0=>0x1]	35	1		T263	2		T331	2		T321	2
all_pins[5]	transitions[0x1=>0x0]	104	1		T263	3		T264	3		T317	1