Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T263	7		T264	4		T317	4
all_values[1]	278	1		T263	7		T264	4		T317	4
all_values[2]	278	1		T263	7		T264	4		T317	4
all_values[3]	278	1		T263	7		T264	4		T317	4
all_values[4]	278	1		T263	7		T264	4		T317	4
all_values[5]	278	1		T263	7		T264	4		T317	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	915	1		T263	22		T264	11		T317	14
auto[1]	753	1		T263	20		T264	13		T317	10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	567	1		T263	15		T264	11		T317	8
auto[1]	1101	1		T263	27		T264	13		T317	16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	995	1		T263	26		T264	17		T317	16
auto[1]	673	1		T263	16		T264	7		T317	8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	82	1		T264	1		T317	3		T318	1
all_values[0]	auto[0]	auto[1]	auto[1]	76	1		T263	5		T264	1		T318	3
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T263	2		T318	1		T319	3
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T264	2		T317	1		T318	2
all_values[1]	auto[0]	auto[0]	auto[1]	92	1		T263	4		T264	2		T318	2
all_values[1]	auto[0]	auto[1]	auto[1]	76	1		T264	1		T317	3		T318	2
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T263	1		T264	1		T318	1
all_values[1]	auto[1]	auto[1]	auto[1]	44	1		T263	2		T317	1		T318	2
all_values[2]	auto[0]	auto[0]	auto[0]	93	1		T263	4		T264	1		T317	2
all_values[2]	auto[0]	auto[1]	auto[0]	64	1		T264	2		T318	2		T319	2
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T263	2		T317	1		T318	2
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T263	1		T264	1		T317	1
all_values[3]	auto[0]	auto[0]	auto[0]	97	1		T263	1		T264	2		T317	1
all_values[3]	auto[0]	auto[1]	auto[0]	80	1		T263	3		T317	2		T318	1
all_values[3]	auto[1]	auto[0]	auto[1]	54	1		T263	1		T264	2		T317	1
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T263	2		T318	1		T320	1
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T263	4		T318	2		T319	1
all_values[4]	auto[0]	auto[0]	auto[1]	20	1		T317	1		T319	2		T320	1
all_values[4]	auto[0]	auto[1]	auto[0]	59	1		T264	2		T317	1		T318	2
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T263	1		T264	1		T319	2
all_values[4]	auto[1]	auto[0]	auto[1]	64	1		T263	2		T317	1		T318	2
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T264	1		T317	1		T318	1
all_values[5]	auto[0]	auto[0]	auto[0]	63	1		T263	1		T264	2		T317	2
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T317	1		T318	2		T319	1
all_values[5]	auto[0]	auto[1]	auto[0]	49	1		T263	2		T264	2		T318	2
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T263	1		T319	1		T321	3
all_values[5]	auto[1]	auto[0]	auto[1]	65	1		T317	1		T318	2		T319	1
all_values[5]	auto[1]	auto[1]	auto[1]	46	1		T263	3		T318	1		T319	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal