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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.74 93.99 98.31 92.52 98.31 96.89 98.09


Total test records in report: 1258
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T1076 /workspace/coverage/default/15.flash_ctrl_disable.1141613174 Aug 16 06:39:26 PM PDT 24 Aug 16 06:39:48 PM PDT 24 21127900 ps
T1077 /workspace/coverage/default/37.flash_ctrl_otp_reset.1871831113 Aug 16 06:41:35 PM PDT 24 Aug 16 06:43:49 PM PDT 24 38676600 ps
T1078 /workspace/coverage/default/18.flash_ctrl_re_evict.3783087718 Aug 16 06:39:51 PM PDT 24 Aug 16 06:40:27 PM PDT 24 126027500 ps
T64 /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.617150061 Aug 16 06:37:03 PM PDT 24 Aug 16 06:37:18 PM PDT 24 16194400 ps
T1079 /workspace/coverage/default/43.flash_ctrl_connect.86584515 Aug 16 06:41:54 PM PDT 24 Aug 16 06:42:10 PM PDT 24 43073000 ps
T1080 /workspace/coverage/default/19.flash_ctrl_smoke.1957425477 Aug 16 06:39:53 PM PDT 24 Aug 16 06:41:34 PM PDT 24 124760200 ps
T1081 /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.42338036 Aug 16 06:37:31 PM PDT 24 Aug 16 06:37:45 PM PDT 24 25521300 ps
T1082 /workspace/coverage/default/48.flash_ctrl_disable.2577817980 Aug 16 06:42:01 PM PDT 24 Aug 16 06:42:23 PM PDT 24 29384600 ps
T1083 /workspace/coverage/default/28.flash_ctrl_alert_test.1939790663 Aug 16 06:41:03 PM PDT 24 Aug 16 06:41:17 PM PDT 24 47737400 ps
T1084 /workspace/coverage/default/13.flash_ctrl_otp_reset.2572523953 Aug 16 06:38:52 PM PDT 24 Aug 16 06:40:41 PM PDT 24 132949900 ps
T1085 /workspace/coverage/default/78.flash_ctrl_connect.4128910084 Aug 16 06:42:32 PM PDT 24 Aug 16 06:42:48 PM PDT 24 239153100 ps
T1086 /workspace/coverage/default/44.flash_ctrl_otp_reset.2772323974 Aug 16 06:41:54 PM PDT 24 Aug 16 06:44:09 PM PDT 24 39251300 ps
T403 /workspace/coverage/default/26.flash_ctrl_disable.287970835 Aug 16 06:40:41 PM PDT 24 Aug 16 06:41:01 PM PDT 24 29055400 ps
T1087 /workspace/coverage/default/14.flash_ctrl_disable.2401085458 Aug 16 06:39:05 PM PDT 24 Aug 16 06:39:27 PM PDT 24 30086400 ps
T1088 /workspace/coverage/default/39.flash_ctrl_intr_rd.2991489163 Aug 16 06:41:33 PM PDT 24 Aug 16 06:43:56 PM PDT 24 749434000 ps
T1089 /workspace/coverage/default/21.flash_ctrl_prog_reset.3573197600 Aug 16 06:40:22 PM PDT 24 Aug 16 06:40:36 PM PDT 24 62526700 ps
T1090 /workspace/coverage/default/3.flash_ctrl_error_prog_type.2349395964 Aug 16 06:37:01 PM PDT 24 Aug 16 07:21:30 PM PDT 24 1585202100 ps
T1091 /workspace/coverage/default/20.flash_ctrl_connect.375662299 Aug 16 06:40:21 PM PDT 24 Aug 16 06:40:36 PM PDT 24 16742300 ps
T1092 /workspace/coverage/default/9.flash_ctrl_error_mp.1594960583 Aug 16 06:38:11 PM PDT 24 Aug 16 07:20:35 PM PDT 24 20832916400 ps
T1093 /workspace/coverage/default/14.flash_ctrl_re_evict.2471841392 Aug 16 06:39:06 PM PDT 24 Aug 16 06:39:41 PM PDT 24 271783500 ps
T1094 /workspace/coverage/default/45.flash_ctrl_alert_test.108451506 Aug 16 06:41:52 PM PDT 24 Aug 16 06:42:06 PM PDT 24 56295000 ps
T1095 /workspace/coverage/default/5.flash_ctrl_invalid_op.4150844445 Aug 16 06:37:22 PM PDT 24 Aug 16 06:38:57 PM PDT 24 4011028900 ps
T253 /workspace/coverage/default/2.flash_ctrl_wr_intg.2244313145 Aug 16 06:37:01 PM PDT 24 Aug 16 06:37:17 PM PDT 24 159381500 ps
T1096 /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2109537170 Aug 16 06:37:05 PM PDT 24 Aug 16 06:37:28 PM PDT 24 106709800 ps
T1097 /workspace/coverage/default/4.flash_ctrl_smoke.1607112184 Aug 16 06:37:00 PM PDT 24 Aug 16 06:38:16 PM PDT 24 30285300 ps
T1098 /workspace/coverage/default/25.flash_ctrl_intr_rd.2927680160 Aug 16 06:40:36 PM PDT 24 Aug 16 06:42:49 PM PDT 24 2806222300 ps
T1099 /workspace/coverage/default/36.flash_ctrl_rw_evict.3207484577 Aug 16 06:41:26 PM PDT 24 Aug 16 06:41:55 PM PDT 24 93339100 ps
T1100 /workspace/coverage/default/0.flash_ctrl_fs_sup.3941051835 Aug 16 06:36:29 PM PDT 24 Aug 16 06:37:09 PM PDT 24 325820600 ps
T1101 /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2561842453 Aug 16 06:40:27 PM PDT 24 Aug 16 06:42:43 PM PDT 24 6893963700 ps
T1102 /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3115450426 Aug 16 06:40:41 PM PDT 24 Aug 16 06:45:22 PM PDT 24 11425045000 ps
T1103 /workspace/coverage/default/38.flash_ctrl_connect.2639456443 Aug 16 06:41:37 PM PDT 24 Aug 16 06:41:51 PM PDT 24 72196300 ps
T1104 /workspace/coverage/default/1.flash_ctrl_mp_regions.1436653654 Aug 16 06:36:47 PM PDT 24 Aug 16 06:49:34 PM PDT 24 23027741400 ps
T1105 /workspace/coverage/default/4.flash_ctrl_connect.4164841999 Aug 16 06:37:18 PM PDT 24 Aug 16 06:37:34 PM PDT 24 49241900 ps
T1106 /workspace/coverage/default/5.flash_ctrl_mp_regions.1465728821 Aug 16 06:37:19 PM PDT 24 Aug 16 06:42:13 PM PDT 24 82936803200 ps
T1107 /workspace/coverage/default/11.flash_ctrl_rand_ops.3075617990 Aug 16 06:38:25 PM PDT 24 Aug 16 06:49:06 PM PDT 24 1057812700 ps
T1108 /workspace/coverage/default/0.flash_ctrl_hw_rma.1558494103 Aug 16 06:36:26 PM PDT 24 Aug 16 07:13:30 PM PDT 24 682316284500 ps
T1109 /workspace/coverage/default/60.flash_ctrl_connect.3128525221 Aug 16 06:42:17 PM PDT 24 Aug 16 06:42:33 PM PDT 24 15755900 ps
T1110 /workspace/coverage/default/43.flash_ctrl_otp_reset.3021868999 Aug 16 06:41:48 PM PDT 24 Aug 16 06:43:39 PM PDT 24 77039200 ps
T1111 /workspace/coverage/default/12.flash_ctrl_wo.3698878565 Aug 16 06:38:47 PM PDT 24 Aug 16 06:41:20 PM PDT 24 3414404500 ps
T1112 /workspace/coverage/default/17.flash_ctrl_rw.3388156210 Aug 16 06:39:48 PM PDT 24 Aug 16 06:50:01 PM PDT 24 5671204900 ps
T1113 /workspace/coverage/default/73.flash_ctrl_otp_reset.3752264549 Aug 16 06:42:30 PM PDT 24 Aug 16 06:44:43 PM PDT 24 227877000 ps
T1114 /workspace/coverage/default/15.flash_ctrl_rand_ops.1404160867 Aug 16 06:39:12 PM PDT 24 Aug 16 06:48:21 PM PDT 24 196277000 ps
T1115 /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3174137375 Aug 16 06:38:58 PM PDT 24 Aug 16 06:39:30 PM PDT 24 48272400 ps
T65 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.270314220 Aug 16 06:16:53 PM PDT 24 Aug 16 06:32:15 PM PDT 24 3239946000 ps
T66 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2348370148 Aug 16 06:16:28 PM PDT 24 Aug 16 06:17:07 PM PDT 24 95830300 ps
T67 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4087261921 Aug 16 06:16:41 PM PDT 24 Aug 16 06:17:15 PM PDT 24 257588100 ps
T263 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1482066871 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:17 PM PDT 24 17286300 ps
T264 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4208132125 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:54 PM PDT 24 164586100 ps
T1116 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.366468264 Aug 16 06:16:30 PM PDT 24 Aug 16 06:16:44 PM PDT 24 16812700 ps
T317 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.366945617 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:09 PM PDT 24 54863600 ps
T318 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3717312189 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:16 PM PDT 24 17563600 ps
T100 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.134718451 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:13 PM PDT 24 213443700 ps
T1117 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.44823859 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:11 PM PDT 24 13830700 ps
T260 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3262030061 Aug 16 06:16:36 PM PDT 24 Aug 16 06:17:16 PM PDT 24 326633300 ps
T101 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3101292956 Aug 16 06:16:46 PM PDT 24 Aug 16 06:29:30 PM PDT 24 842170500 ps
T216 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2383728798 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:56 PM PDT 24 44984100 ps
T240 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3826847967 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:16 PM PDT 24 731194600 ps
T319 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.581837062 Aug 16 06:16:59 PM PDT 24 Aug 16 06:17:12 PM PDT 24 15997700 ps
T320 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3572780830 Aug 16 06:16:44 PM PDT 24 Aug 16 06:16:58 PM PDT 24 42903400 ps
T241 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3707012341 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:08 PM PDT 24 44524900 ps
T218 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1596809795 Aug 16 06:16:39 PM PDT 24 Aug 16 06:24:18 PM PDT 24 215658000 ps
T217 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4063900694 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:04 PM PDT 24 468536100 ps
T1118 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.508894199 Aug 16 06:17:00 PM PDT 24 Aug 16 06:17:14 PM PDT 24 17124000 ps
T227 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.292009511 Aug 16 06:16:54 PM PDT 24 Aug 16 06:23:27 PM PDT 24 891865100 ps
T428 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.806645218 Aug 16 06:16:27 PM PDT 24 Aug 16 06:17:13 PM PDT 24 1123828400 ps
T1119 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3044656522 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:55 PM PDT 24 30859900 ps
T1120 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1040276716 Aug 16 06:16:32 PM PDT 24 Aug 16 06:16:48 PM PDT 24 17609000 ps
T1121 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1195471793 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:17 PM PDT 24 30615500 ps
T219 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.202565546 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:58 PM PDT 24 141125200 ps
T1122 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1470025965 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:57 PM PDT 24 47737700 ps
T242 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2551837913 Aug 16 06:16:49 PM PDT 24 Aug 16 06:17:08 PM PDT 24 415749000 ps
T228 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1405805543 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:00 PM PDT 24 57383100 ps
T243 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.583185649 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:13 PM PDT 24 150452600 ps
T331 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.305796913 Aug 16 06:17:00 PM PDT 24 Aug 16 06:17:14 PM PDT 24 26385100 ps
T229 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2096848303 Aug 16 06:16:41 PM PDT 24 Aug 16 06:17:01 PM PDT 24 108197900 ps
T1123 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3208241986 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:16 PM PDT 24 52829100 ps
T244 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.898964532 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:01 PM PDT 24 28168400 ps
T1124 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2937416256 Aug 16 06:16:56 PM PDT 24 Aug 16 06:17:12 PM PDT 24 71215100 ps
T321 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4127089051 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:09 PM PDT 24 14799600 ps
T245 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2763769379 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:07 PM PDT 24 68858200 ps
T1125 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.26139325 Aug 16 06:16:56 PM PDT 24 Aug 16 06:17:12 PM PDT 24 14489300 ps
T246 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3926554696 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:10 PM PDT 24 65149200 ps
T1126 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3546852906 Aug 16 06:17:04 PM PDT 24 Aug 16 06:17:17 PM PDT 24 30819000 ps
T1127 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3940799599 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:08 PM PDT 24 19853700 ps
T230 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4098337794 Aug 16 06:16:46 PM PDT 24 Aug 16 06:24:30 PM PDT 24 701985800 ps
T1128 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2551396962 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:55 PM PDT 24 34652700 ps
T1129 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3127799560 Aug 16 06:16:44 PM PDT 24 Aug 16 06:16:57 PM PDT 24 19150800 ps
T1130 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1039070538 Aug 16 06:17:06 PM PDT 24 Aug 16 06:17:20 PM PDT 24 54308100 ps
T247 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4089796978 Aug 16 06:16:48 PM PDT 24 Aug 16 06:17:05 PM PDT 24 95602100 ps
T231 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2364540927 Aug 16 06:16:47 PM PDT 24 Aug 16 06:17:04 PM PDT 24 135135900 ps
T248 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1474276958 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:09 PM PDT 24 136670100 ps
T1131 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.753695290 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:01 PM PDT 24 25576200 ps
T235 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1638029047 Aug 16 06:16:37 PM PDT 24 Aug 16 06:16:51 PM PDT 24 46101200 ps
T234 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2475197138 Aug 16 06:16:39 PM PDT 24 Aug 16 06:31:49 PM PDT 24 2279980500 ps
T1132 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.904494253 Aug 16 06:16:49 PM PDT 24 Aug 16 06:17:07 PM PDT 24 200579200 ps
T1133 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2531551386 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:16 PM PDT 24 18442500 ps
T1134 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2065800256 Aug 16 06:16:48 PM PDT 24 Aug 16 06:17:18 PM PDT 24 163726700 ps
T1135 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1537968545 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:16 PM PDT 24 18360400 ps
T232 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4215470971 Aug 16 06:16:42 PM PDT 24 Aug 16 06:17:02 PM PDT 24 1220794400 ps
T233 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1836041683 Aug 16 06:16:30 PM PDT 24 Aug 16 06:16:49 PM PDT 24 316420400 ps
T262 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1104836467 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:03 PM PDT 24 320561000 ps
T257 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.83518883 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:11 PM PDT 24 56322300 ps
T1136 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.78022710 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:08 PM PDT 24 23878500 ps
T358 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4049579754 Aug 16 06:16:54 PM PDT 24 Aug 16 06:29:38 PM PDT 24 930657200 ps
T298 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2672672984 Aug 16 06:16:40 PM PDT 24 Aug 16 06:16:56 PM PDT 24 76533600 ps
T265 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3113136226 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:58 PM PDT 24 73754700 ps
T299 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1423413154 Aug 16 06:16:35 PM PDT 24 Aug 16 06:16:52 PM PDT 24 154837800 ps
T1137 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1162943815 Aug 16 06:16:56 PM PDT 24 Aug 16 06:17:13 PM PDT 24 148526400 ps
T1138 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3339383701 Aug 16 06:16:42 PM PDT 24 Aug 16 06:17:03 PM PDT 24 69215300 ps
T360 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3562142817 Aug 16 06:16:46 PM PDT 24 Aug 16 06:23:15 PM PDT 24 368489400 ps
T1139 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1003512028 Aug 16 06:16:51 PM PDT 24 Aug 16 06:17:06 PM PDT 24 36439400 ps
T1140 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.184580864 Aug 16 06:16:49 PM PDT 24 Aug 16 06:17:05 PM PDT 24 23593600 ps
T1141 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3469576547 Aug 16 06:16:40 PM PDT 24 Aug 16 06:16:53 PM PDT 24 21336400 ps
T1142 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2314996039 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:10 PM PDT 24 19313600 ps
T1143 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4131860524 Aug 16 06:16:56 PM PDT 24 Aug 16 06:17:10 PM PDT 24 22357900 ps
T236 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3230584895 Aug 16 06:16:42 PM PDT 24 Aug 16 06:16:56 PM PDT 24 21634200 ps
T1144 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2959367701 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:55 PM PDT 24 276790900 ps
T1145 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3474733634 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:06 PM PDT 24 14192200 ps
T300 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3634024568 Aug 16 06:16:41 PM PDT 24 Aug 16 06:17:57 PM PDT 24 31913026300 ps
T237 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.793067930 Aug 16 06:16:27 PM PDT 24 Aug 16 06:16:41 PM PDT 24 51738700 ps
T1146 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2745845847 Aug 16 06:16:36 PM PDT 24 Aug 16 06:17:32 PM PDT 24 908513900 ps
T1147 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2714013091 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:27 PM PDT 24 238797600 ps
T1148 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1259461611 Aug 16 06:16:37 PM PDT 24 Aug 16 06:16:51 PM PDT 24 45719200 ps
T1149 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3067822853 Aug 16 06:16:44 PM PDT 24 Aug 16 06:17:01 PM PDT 24 62883600 ps
T1150 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1791742966 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:16 PM PDT 24 51511100 ps
T1151 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.270185205 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:02 PM PDT 24 25038500 ps
T1152 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1968789817 Aug 16 06:16:28 PM PDT 24 Aug 16 06:16:41 PM PDT 24 19195800 ps
T1153 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.411657126 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:08 PM PDT 24 17810900 ps
T1154 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2147980336 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:08 PM PDT 24 54999300 ps
T301 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3243758837 Aug 16 06:16:39 PM PDT 24 Aug 16 06:17:24 PM PDT 24 3429372400 ps
T273 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1036223604 Aug 16 06:16:51 PM PDT 24 Aug 16 06:17:08 PM PDT 24 191449800 ps
T1155 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.778467010 Aug 16 06:17:05 PM PDT 24 Aug 16 06:17:19 PM PDT 24 22058400 ps
T1156 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.497529970 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:16 PM PDT 24 163181700 ps
T261 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1122218654 Aug 16 06:16:29 PM PDT 24 Aug 16 06:16:50 PM PDT 24 174058000 ps
T302 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2214476294 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:59 PM PDT 24 99630100 ps
T1157 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2575214363 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:00 PM PDT 24 13512600 ps
T1158 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4185668605 Aug 16 06:16:44 PM PDT 24 Aug 16 06:17:01 PM PDT 24 40232900 ps
T1159 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3424124871 Aug 16 06:17:05 PM PDT 24 Aug 16 06:17:19 PM PDT 24 24879800 ps
T1160 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.872865961 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:14 PM PDT 24 122216300 ps
T1161 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2402335008 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:53 PM PDT 24 26398500 ps
T1162 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3640232500 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:03 PM PDT 24 65054700 ps
T1163 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1635413942 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:16 PM PDT 24 16716200 ps
T1164 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.619703745 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:29 PM PDT 24 1505017700 ps
T1165 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3165935334 Aug 16 06:16:27 PM PDT 24 Aug 16 06:16:45 PM PDT 24 73960200 ps
T1166 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3944639748 Aug 16 06:16:38 PM PDT 24 Aug 16 06:16:53 PM PDT 24 184641800 ps
T267 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1029293500 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:12 PM PDT 24 114444400 ps
T357 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2830418182 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:10 PM PDT 24 66192000 ps
T271 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2572438525 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:10 PM PDT 24 163435300 ps
T1167 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1080440343 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:09 PM PDT 24 87532300 ps
T266 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1695871090 Aug 16 06:16:50 PM PDT 24 Aug 16 06:29:35 PM PDT 24 3370650000 ps
T1168 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3775571186 Aug 16 06:16:38 PM PDT 24 Aug 16 06:16:52 PM PDT 24 14914800 ps
T1169 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3250475797 Aug 16 06:16:59 PM PDT 24 Aug 16 06:17:13 PM PDT 24 62486500 ps
T1170 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2046288938 Aug 16 06:16:44 PM PDT 24 Aug 16 06:16:57 PM PDT 24 19730000 ps
T361 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.233508673 Aug 16 06:16:41 PM PDT 24 Aug 16 06:31:49 PM PDT 24 2034517300 ps
T1171 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1232577573 Aug 16 06:16:44 PM PDT 24 Aug 16 06:17:01 PM PDT 24 26352600 ps
T1172 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3469333210 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:17 PM PDT 24 89036000 ps
T1173 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2759342966 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:54 PM PDT 24 15039000 ps
T269 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.131149610 Aug 16 06:16:49 PM PDT 24 Aug 16 06:17:05 PM PDT 24 61681900 ps
T1174 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2314468654 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:16 PM PDT 24 39089700 ps
T268 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1258978757 Aug 16 06:16:28 PM PDT 24 Aug 16 06:24:16 PM PDT 24 171956100 ps
T1175 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.541938531 Aug 16 06:16:38 PM PDT 24 Aug 16 06:16:51 PM PDT 24 17653800 ps
T1176 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3054701217 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:55 PM PDT 24 19262000 ps
T1177 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1878898876 Aug 16 06:16:39 PM PDT 24 Aug 16 06:17:10 PM PDT 24 33527200 ps
T363 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3107939274 Aug 16 06:16:55 PM PDT 24 Aug 16 06:24:28 PM PDT 24 559366500 ps
T270 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2870408234 Aug 16 06:16:51 PM PDT 24 Aug 16 06:17:11 PM PDT 24 125172500 ps
T303 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2393021112 Aug 16 06:16:28 PM PDT 24 Aug 16 06:16:44 PM PDT 24 245947300 ps
T1178 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2292500029 Aug 16 06:16:40 PM PDT 24 Aug 16 06:16:53 PM PDT 24 15256100 ps
T1179 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1826556635 Aug 16 06:16:38 PM PDT 24 Aug 16 06:17:24 PM PDT 24 163425900 ps
T272 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1964822003 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:57 PM PDT 24 45127700 ps
T1180 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1289821193 Aug 16 06:16:45 PM PDT 24 Aug 16 06:16:59 PM PDT 24 15260200 ps
T1181 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2671704019 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:06 PM PDT 24 15203600 ps
T1182 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2085104838 Aug 16 06:16:59 PM PDT 24 Aug 16 06:17:12 PM PDT 24 72098500 ps
T1183 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1914718639 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:16 PM PDT 24 18957800 ps
T1184 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2679159568 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:09 PM PDT 24 51325400 ps
T1185 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4271325942 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:11 PM PDT 24 41288900 ps
T1186 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2914235798 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:03 PM PDT 24 43822400 ps
T1187 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1555795944 Aug 16 06:16:55 PM PDT 24 Aug 16 06:17:09 PM PDT 24 26529700 ps
T238 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2694688684 Aug 16 06:16:33 PM PDT 24 Aug 16 06:16:46 PM PDT 24 45498300 ps
T1188 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2544745310 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:58 PM PDT 24 250964300 ps
T1189 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3519242518 Aug 16 06:16:41 PM PDT 24 Aug 16 06:31:58 PM PDT 24 1354722900 ps
T1190 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4080990138 Aug 16 06:16:56 PM PDT 24 Aug 16 06:17:09 PM PDT 24 57193600 ps
T1191 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3399106195 Aug 16 06:16:28 PM PDT 24 Aug 16 06:16:42 PM PDT 24 31597800 ps
T1192 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2914219172 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:12 PM PDT 24 74726100 ps
T1193 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.998138 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:52 PM PDT 24 15291600 ps
T1194 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1318696274 Aug 16 06:16:37 PM PDT 24 Aug 16 06:16:57 PM PDT 24 57387700 ps
T1195 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.501145675 Aug 16 06:16:51 PM PDT 24 Aug 16 06:17:04 PM PDT 24 53482000 ps
T1196 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3707394865 Aug 16 06:16:57 PM PDT 24 Aug 16 06:17:17 PM PDT 24 81014000 ps
T359 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1817936949 Aug 16 06:16:26 PM PDT 24 Aug 16 06:24:09 PM PDT 24 181620700 ps
T1197 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4143668140 Aug 16 06:17:05 PM PDT 24 Aug 16 06:17:18 PM PDT 24 16367100 ps
T364 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2938722748 Aug 16 06:16:46 PM PDT 24 Aug 16 06:32:00 PM PDT 24 341177500 ps
T1198 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.943624784 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:09 PM PDT 24 451152500 ps
T1199 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1912237203 Aug 16 06:16:27 PM PDT 24 Aug 16 06:16:41 PM PDT 24 139343900 ps
T1200 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2099091621 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:10 PM PDT 24 38807500 ps
T365 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2544422892 Aug 16 06:16:53 PM PDT 24 Aug 16 06:32:06 PM PDT 24 373154600 ps
T1201 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4030010309 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:15 PM PDT 24 26911800 ps
T1202 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3180445592 Aug 16 06:16:35 PM PDT 24 Aug 16 06:16:48 PM PDT 24 177271800 ps
T1203 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2974117644 Aug 16 06:16:49 PM PDT 24 Aug 16 06:17:03 PM PDT 24 56753800 ps
T304 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2288507293 Aug 16 06:16:33 PM PDT 24 Aug 16 06:17:20 PM PDT 24 54065800 ps
T366 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.797539807 Aug 16 06:16:40 PM PDT 24 Aug 16 06:29:20 PM PDT 24 853576100 ps
T1204 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3097147718 Aug 16 06:16:44 PM PDT 24 Aug 16 06:16:59 PM PDT 24 111356500 ps
T362 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3614851971 Aug 16 06:16:40 PM PDT 24 Aug 16 06:31:44 PM PDT 24 1161452300 ps
T1205 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3536513930 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:17 PM PDT 24 88182700 ps
T1206 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3311128313 Aug 16 06:17:06 PM PDT 24 Aug 16 06:17:19 PM PDT 24 52114000 ps
T1207 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1030817343 Aug 16 06:16:37 PM PDT 24 Aug 16 06:16:56 PM PDT 24 108459000 ps
T1208 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.34582955 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:00 PM PDT 24 115611100 ps
T1209 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1250126851 Aug 16 06:17:02 PM PDT 24 Aug 16 06:17:15 PM PDT 24 41141700 ps
T1210 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4284661566 Aug 16 06:16:43 PM PDT 24 Aug 16 06:16:58 PM PDT 24 12275500 ps
T1211 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.612481602 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:00 PM PDT 24 33651900 ps
T305 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2096053959 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:01 PM PDT 24 257835600 ps
T1212 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.679899596 Aug 16 06:16:29 PM PDT 24 Aug 16 06:17:30 PM PDT 24 2622902700 ps
T1213 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2882270633 Aug 16 06:16:28 PM PDT 24 Aug 16 06:16:42 PM PDT 24 16405100 ps
T1214 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2642328248 Aug 16 06:17:04 PM PDT 24 Aug 16 06:17:17 PM PDT 24 16646000 ps
T1215 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3720134853 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:54 PM PDT 24 31683500 ps
T1216 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1795908785 Aug 16 06:16:30 PM PDT 24 Aug 16 06:17:23 PM PDT 24 440934900 ps
T1217 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2687898463 Aug 16 06:16:27 PM PDT 24 Aug 16 06:16:43 PM PDT 24 15134000 ps
T1218 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3530631697 Aug 16 06:16:29 PM PDT 24 Aug 16 06:16:50 PM PDT 24 56883300 ps
T1219 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3576785042 Aug 16 06:17:03 PM PDT 24 Aug 16 06:17:17 PM PDT 24 43812200 ps
T1220 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3219599390 Aug 16 06:16:51 PM PDT 24 Aug 16 06:17:09 PM PDT 24 298699200 ps
T1221 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2457663094 Aug 16 06:16:52 PM PDT 24 Aug 16 06:17:11 PM PDT 24 102651400 ps
T1222 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3892595083 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:04 PM PDT 24 53247700 ps
T1223 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1435854270 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:54 PM PDT 24 60546000 ps
T1224 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4195150868 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:14 PM PDT 24 316076300 ps
T1225 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3088572258 Aug 16 06:16:37 PM PDT 24 Aug 16 06:17:08 PM PDT 24 19524300 ps
T1226 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2999353769 Aug 16 06:16:36 PM PDT 24 Aug 16 06:16:50 PM PDT 24 14421100 ps
T1227 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1061781091 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:08 PM PDT 24 17633500 ps
T1228 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2087111831 Aug 16 06:16:45 PM PDT 24 Aug 16 06:17:01 PM PDT 24 17399300 ps
T239 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1185911893 Aug 16 06:16:39 PM PDT 24 Aug 16 06:16:53 PM PDT 24 29857400 ps
T1229 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1927138834 Aug 16 06:16:45 PM PDT 24 Aug 16 06:16:59 PM PDT 24 41505200 ps
T1230 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3851848852 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:59 PM PDT 24 226417400 ps
T1231 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1213109949 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:13 PM PDT 24 396387000 ps
T1232 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1039288163 Aug 16 06:16:38 PM PDT 24 Aug 16 06:16:56 PM PDT 24 385624800 ps
T1233 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3297698086 Aug 16 06:16:38 PM PDT 24 Aug 16 06:16:58 PM PDT 24 355338500 ps
T1234 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2270728545 Aug 16 06:16:44 PM PDT 24 Aug 16 06:17:02 PM PDT 24 69986100 ps
T1235 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3195055760 Aug 16 06:16:53 PM PDT 24 Aug 16 06:17:06 PM PDT 24 22288100 ps
T1236 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1723525028 Aug 16 06:16:56 PM PDT 24 Aug 16 06:29:27 PM PDT 24 750722900 ps
T1237 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1974106669 Aug 16 06:16:46 PM PDT 24 Aug 16 06:17:03 PM PDT 24 33891500 ps
T1238 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.495450687 Aug 16 06:16:58 PM PDT 24 Aug 16 06:17:17 PM PDT 24 88004900 ps
T1239 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2089066943 Aug 16 06:16:27 PM PDT 24 Aug 16 06:17:15 PM PDT 24 419502700 ps
T1240 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.80571327 Aug 16 06:16:45 PM PDT 24 Aug 16 06:16:58 PM PDT 24 12605300 ps
T1241 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1371863239 Aug 16 06:16:40 PM PDT 24 Aug 16 06:16:57 PM PDT 24 77914000 ps
T1242 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.138618994 Aug 16 06:16:42 PM PDT 24 Aug 16 06:17:25 PM PDT 24 1590187100 ps
T1243 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.83353958 Aug 16 06:16:54 PM PDT 24 Aug 16 06:17:10 PM PDT 24 16058600 ps
T1244 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1702328631 Aug 16 06:16:27 PM PDT 24 Aug 16 06:16:41 PM PDT 24 28746600 ps
T1245 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2119669291 Aug 16 06:16:36 PM PDT 24 Aug 16 06:16:53 PM PDT 24 60035100 ps
T1246 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1388966219 Aug 16 06:16:41 PM PDT 24 Aug 16 06:16:56 PM PDT 24 19673200 ps
T306 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3606066528 Aug 16 06:16:27 PM PDT 24 Aug 16 06:16:46 PM PDT 24 459432800 ps
T1247 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1712557630 Aug 16 06:16:43 PM PDT 24 Aug 16 06:16:57 PM PDT 24 20791500 ps
T1248 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2788021004 Aug 16 06:16:42 PM PDT 24 Aug 16 06:17:12 PM PDT 24 125771700 ps
T1249 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2851008086 Aug 16 06:16:40 PM PDT 24 Aug 16 06:17:01 PM PDT 24 70138600 ps
T1250 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4163655908 Aug 16 06:16:40 PM PDT 24 Aug 16 06:16:57 PM PDT 24 38716900 ps
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