Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333297	1		T1	1		T2	1		T3	2
all_values[1]	333297	1		T1	1		T2	1		T3	2
all_values[2]	333297	1		T1	1		T2	1		T3	2
all_values[3]	333297	1		T1	1		T2	1		T3	2
all_values[4]	333297	1		T1	1		T2	1		T3	2
all_values[5]	333297	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	672781	1		T1	6		T2	6		T3	12
auto[1]	1327001	1		T7	14768		T8	12712		T22	6864

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	977968	1		T1	4		T2	4		T3	7
auto[1]	1021814	1		T1	2		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	333125	1		T1	1		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	172	1		T244	1		T246	3		T311	2
all_values[1]	auto[0]	auto[1]	333134	1		T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	163	1		T245	3		T246	2		T311	6
all_values[2]	auto[0]	auto[0]	1559	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	55	1		T311	2		T309	1		T310	2
all_values[2]	auto[1]	auto[0]	331620	1		T7	3692		T8	3178		T22	1716
all_values[2]	auto[1]	auto[1]	63	1		T246	2		T311	3		T308	1
all_values[3]	auto[0]	auto[0]	1580	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	48	1		T245	1		T309	1		T313	1
all_values[3]	auto[1]	auto[0]	83711	1		T7	1846		T8	1589		T22	1716
all_values[3]	auto[1]	auto[1]	247958	1		T7	1846		T8	1589		T35	4788
all_values[4]	auto[0]	auto[0]	1114	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	525	1		T3	1		T4	1		T5	1
all_values[4]	auto[1]	auto[0]	225244	1		T7	1846		T8	1589		T22	1
all_values[4]	auto[1]	auto[1]	106414	1		T7	1846		T8	1589		T22	1715
all_values[5]	auto[0]	auto[0]	1541	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	100	1		T20	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	331599	1		T7	3692		T8	3178		T22	1716
all_values[5]	auto[1]	auto[1]	57	1		T244	1		T246	1		T311	1