Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	244436	1		T3	732		T4	1		T5	402
auto[FlashEraseBank]	268648	1		T3	933		T4	2		T16	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	253040	1		T3	635		T5	7		T6	747
auto[FlashOpProgram]	240091	1		T3	1030		T4	2		T5	384
auto[FlashOpErase]	15953	1		T4	1		T5	11		T6	378
auto[FlashOpInvalid]	4000	1		T44	200		T130	200		T277	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	253040	1		T3	635		T5	7		T6	747
op[FlashOpProgram]	240091	1		T3	1030		T4	2		T5	384
op[FlashOpErase]	15953	1		T4	1		T5	11		T6	378
read_erase_read	587	1		T5	1		T30	3		T24	13
read_prog_read	817	1		T3	1		T30	3		T38	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	369936	1		T3	1528		T4	3		T16	1
auto[FlashPartInfo]	139792	1		T3	132		T5	402		T6	1503
auto[FlashPartInfo1]	740	1		T30	1		T40	4		T41	3
auto[FlashPartInfo2]	2616	1		T3	5		T54	7		T61	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	181777	1		T3	543		T7	1846		T30	33
auto[FlashPartData]	auto[FlashOpProgram]	180686	1		T3	985		T4	2		T16	1
auto[FlashPartData]	auto[FlashOpErase]	3573	1		T4	1		T30	30		T44	95
auto[FlashPartData]	auto[FlashOpInvalid]	3900	1		T44	190		T130	194		T277	196
auto[FlashPartInfo]	auto[FlashOpRead]	69110	1		T3	88		T5	7		T6	747
auto[FlashPartInfo]	auto[FlashOpProgram]	58241	1		T3	44		T5	384		T6	378
auto[FlashPartInfo]	auto[FlashOpErase]	12351	1		T5	11		T6	378		T30	13
auto[FlashPartInfo]	auto[FlashOpInvalid]	90	1		T44	10		T130	4		T277	4
auto[FlashPartInfo1]	auto[FlashOpRead]	568	1		T40	4		T41	3		T36	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T30	1		T130	1		T112	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T130	1		T116	1		T117	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T130	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1585	1		T3	4		T40	13		T20	10
auto[FlashPartInfo2]	auto[FlashOpProgram]	999	1		T3	1		T54	7		T61	7
auto[FlashPartInfo2]	auto[FlashOpErase]	24	1		T127	1		T98	1		T135	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T136	2		T400	2		T401	2