Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31471	1		T6	756		T44	400		T57	568
auto[1]	60	1		T129	9		T265	2		T139	10
auto[2]	75	1		T70	8		T257	19		T139	5
auto[3]	252	1		T24	7		T41	1		T27	10

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7966	1		T6	189		T44	100		T24	2
evic_idx[1]	7973	1		T6	189		T44	100		T24	2
evic_idx[2]	7961	1		T6	189		T44	100		T24	1
evic_idx[3]	7958	1		T6	189		T44	100		T24	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30938	1		T6	756		T44	400		T24	7
evic_op[2]	312	1		T19	16		T41	1		T25	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[2] , evic_idx[3]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7657	1		T6	189		T44	100		T57	142
evic_idx[0]	evic_op[1]	auto[1]	13	1		T129	3		T139	2		T331	2
evic_idx[0]	evic_op[1]	auto[2]	13	1		T257	6		T139	2		T332	1
evic_idx[0]	evic_op[1]	auto[3]	56	1		T24	2		T27	3		T129	1
evic_idx[0]	evic_op[2]	auto[0]	62	1		T19	4		T220	1		T242	2
evic_idx[0]	evic_op[2]	auto[1]	4	1		T258	1		T333	1		T260	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T41	1		T198	1		T334	1
evic_idx[1]	evic_op[1]	auto[0]	7658	1		T6	189		T44	100		T57	142
evic_idx[1]	evic_op[1]	auto[1]	12	1		T129	2		T139	2		T331	2
evic_idx[1]	evic_op[1]	auto[2]	14	1		T257	6		T139	1		T331	1
evic_idx[1]	evic_op[1]	auto[3]	55	1		T24	2		T27	2		T129	2
evic_idx[1]	evic_op[2]	auto[0]	67	1		T19	4		T220	1		T242	2
evic_idx[1]	evic_op[2]	auto[1]	3	1		T265	1		T258	1		T335	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T336	1		T337	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T338	1		T307	1		T339	1
evic_idx[2]	evic_op[1]	auto[0]	7659	1		T6	189		T44	100		T57	142
evic_idx[2]	evic_op[1]	auto[1]	12	1		T129	2		T139	3		T331	2
evic_idx[2]	evic_op[1]	auto[2]	9	1		T257	4		T139	1		T332	1
evic_idx[2]	evic_op[1]	auto[3]	54	1		T24	1		T27	3		T129	2
evic_idx[2]	evic_op[2]	auto[0]	63	1		T19	4		T220	1		T242	2
evic_idx[2]	evic_op[2]	auto[1]	3	1		T265	1		T340	1		T341	1
evic_idx[2]	evic_op[2]	auto[3]	9	1		T342	1		T343	1		T344	1
evic_idx[3]	evic_op[1]	auto[0]	7658	1		T6	189		T44	100		T57	142
evic_idx[3]	evic_op[1]	auto[1]	11	1		T129	2		T139	3		T331	3
evic_idx[3]	evic_op[1]	auto[2]	9	1		T257	3		T139	1		T331	1
evic_idx[3]	evic_op[1]	auto[3]	48	1		T24	2		T27	2		T257	1
evic_idx[3]	evic_op[2]	auto[0]	67	1		T19	4		T220	1		T242	2
evic_idx[3]	evic_op[2]	auto[1]	2	1		T345	1		T346	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T25	1		T26	1		T347	1