Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35461	1		T83	14730		T315	2659		T316	14141
rd_lvl[2]	31661	1		T83	10769		T317	1322		T318	1142
rd_lvl[3]	10213	1		T262	1126		T319	713		T320	1176
rd_lvl[4]	30226	1		T145	5149		T262	1101		T319	1839
rd_lvl[5]	14896	1		T35	2194		T145	954		T83	1
rd_lvl[6]	10909	1		T35	1230		T262	46		T321	2575
rd_lvl[7]	13029	1		T35	50		T146	622		T120	386
rd_lvl[8]	21145	1		T146	316		T120	322		T123	3129
rd_lvl[9]	7882	1		T146	70		T120	258		T123	247
rd_lvl[10]	9445	1		T7	1327		T8	1265		T146	70
rd_lvl[11]	6546	1		T7	519		T8	324		T322	481
rd_lvl[12]	9820	1		T322	1075		T323	152		T324	381
rd_lvl[13]	3076	1		T32	352		T262	12		T325	569
rd_lvl[14]	5506	1		T32	1160		T325	1154		T34	127
rd_lvl[15]	1506	1		T33	240		T326	67		T327	33