Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	333297	1		T1	1		T2	1		T3	2
all_pins[1]	333297	1		T1	1		T2	1		T3	2
all_pins[2]	333297	1		T1	1		T2	1		T3	2
all_pins[3]	333297	1		T1	1		T2	1		T3	2
all_pins[4]	333297	1		T1	1		T2	1		T3	2
all_pins[5]	333297	1		T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1668737	1		T1	6		T2	6		T3	12
values[0x1]	331045	1		T7	3692		T8	3178		T22	1715
transitions[0x0=>0x1]	298600	1		T7	3692		T8	3178		T22	1715
transitions[0x1=>0x0]	298584	1		T7	3692		T8	3178		T22	1715

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	333125	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	172	1		T244	1		T246	3		T311	2
all_pins[0]	transitions[0x0=>0x1]	85	1		T244	1		T246	3		T308	1
all_pins[0]	transitions[0x1=>0x0]	76	1		T245	3		T246	2		T311	4
all_pins[1]	values[0x0]	333134	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	163	1		T245	3		T246	2		T311	6
all_pins[1]	transitions[0x0=>0x1]	132	1		T245	3		T246	1		T311	3
all_pins[1]	transitions[0x1=>0x0]	2440	1		T33	1116		T326	13		T348	1029
all_pins[2]	values[0x0]	330826	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	2471	1		T33	1116		T326	13		T348	1029
all_pins[2]	transitions[0x0=>0x1]	47	1		T246	2		T311	1		T308	1
all_pins[2]	transitions[0x1=>0x0]	211919	1		T7	1846		T8	1589		T35	3474
all_pins[3]	values[0x0]	118954	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	214343	1		T7	1846		T8	1589		T35	3474
all_pins[3]	transitions[0x0=>0x1]	184494	1		T7	1846		T8	1589		T35	3367
all_pins[3]	transitions[0x1=>0x0]	83990	1		T7	1846		T8	1589		T22	1715
all_pins[4]	values[0x0]	219458	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	113839	1		T7	1846		T8	1589		T22	1715
all_pins[4]	transitions[0x0=>0x1]	113825	1		T7	1846		T8	1589		T22	1715
all_pins[4]	transitions[0x1=>0x0]	43	1		T246	1		T308	1		T309	2
all_pins[5]	values[0x0]	333240	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	57	1		T244	1		T246	1		T311	1
all_pins[5]	transitions[0x0=>0x1]	17	1		T308	1		T309	1		T310	1
all_pins[5]	transitions[0x1=>0x0]	116	1		T246	2		T311	2		T308	1