Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T244 4 T245 4 T246 4
all_values[1] 278 1 T244 4 T245 4 T246 4
all_values[2] 278 1 T244 4 T245 4 T246 4
all_values[3] 278 1 T244 4 T245 4 T246 4
all_values[4] 278 1 T244 4 T245 4 T246 4
all_values[5] 278 1 T244 4 T245 4 T246 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 888 1 T244 16 T245 12 T246 13
auto[1] 780 1 T244 8 T245 12 T246 11



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 551 1 T244 10 T245 12 T246 9
auto[1] 1117 1 T244 14 T245 12 T246 15



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 976 1 T244 17 T245 17 T246 17
auto[1] 692 1 T244 7 T245 7 T246 7



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 90 1 T244 2 T245 3 T246 2
all_values[0] auto[0] auto[1] auto[1] 83 1 T244 1 T246 1 T308 1
all_values[0] auto[1] auto[0] auto[1] 52 1 T244 1 T245 1 T246 1
all_values[0] auto[1] auto[1] auto[1] 53 1 T308 1 T309 2 T310 1
all_values[1] auto[0] auto[0] auto[1] 76 1 T244 2 T245 1 T246 1
all_values[1] auto[0] auto[1] auto[1] 78 1 T245 1 T246 2 T311 3
all_values[1] auto[1] auto[0] auto[1] 59 1 T244 2 T245 1 T308 3
all_values[1] auto[1] auto[1] auto[1] 65 1 T245 1 T246 1 T311 2
all_values[2] auto[0] auto[0] auto[0] 87 1 T244 3 T245 1 T311 2
all_values[2] auto[0] auto[1] auto[0] 73 1 T244 1 T245 3 T246 2
all_values[2] auto[1] auto[0] auto[1] 62 1 T311 2 T308 1 T309 1
all_values[2] auto[1] auto[1] auto[1] 56 1 T246 2 T311 3 T309 2
all_values[3] auto[0] auto[0] auto[0] 100 1 T244 1 T246 4 T311 2
all_values[3] auto[0] auto[1] auto[0] 75 1 T244 2 T245 3 T311 2
all_values[3] auto[1] auto[0] auto[1] 51 1 T245 1 T311 1 T309 1
all_values[3] auto[1] auto[1] auto[1] 52 1 T244 1 T311 2 T308 1
all_values[4] auto[0] auto[0] auto[0] 55 1 T244 2 T245 1 T311 2
all_values[4] auto[0] auto[0] auto[1] 28 1 T246 1 T311 1 T308 2
all_values[4] auto[0] auto[1] auto[0] 52 1 T245 2 T246 1 T309 1
all_values[4] auto[0] auto[1] auto[1] 19 1 T244 1 T309 1 T312 1
all_values[4] auto[1] auto[0] auto[1] 67 1 T244 1 T245 1 T246 1
all_values[4] auto[1] auto[1] auto[1] 57 1 T246 1 T311 4 T309 3
all_values[5] auto[0] auto[0] auto[0] 59 1 T245 1 T246 2 T309 2
all_values[5] auto[0] auto[0] auto[1] 31 1 T244 1 T246 1 T308 1
all_values[5] auto[0] auto[1] auto[0] 50 1 T244 1 T245 1 T311 3
all_values[5] auto[0] auto[1] auto[1] 20 1 T310 2 T313 1 T314 1
all_values[5] auto[1] auto[0] auto[1] 71 1 T244 1 T245 1 T311 2
all_values[5] auto[1] auto[1] auto[1] 47 1 T244 1 T245 1 T246 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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