| T1074 |
/workspace/coverage/default/28.flash_ctrl_disable.312315333 |
|
|
Aug 17 06:42:14 PM PDT 24 |
Aug 17 06:42:35 PM PDT 24 |
17997200 ps |
| T1075 |
/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3031342041 |
|
|
Aug 17 06:39:40 PM PDT 24 |
Aug 17 06:42:53 PM PDT 24 |
46186323500 ps |
| T1076 |
/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.514778994 |
|
|
Aug 17 06:39:58 PM PDT 24 |
Aug 17 06:42:06 PM PDT 24 |
17373132700 ps |
| T1077 |
/workspace/coverage/default/19.flash_ctrl_rand_ops.3030287901 |
|
|
Aug 17 06:41:31 PM PDT 24 |
Aug 17 07:01:53 PM PDT 24 |
623989300 ps |
| T1078 |
/workspace/coverage/default/3.flash_ctrl_ro_serr.2300092103 |
|
|
Aug 17 06:40:03 PM PDT 24 |
Aug 17 06:42:18 PM PDT 24 |
3806038400 ps |
| T1079 |
/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2175205181 |
|
|
Aug 17 06:40:17 PM PDT 24 |
Aug 17 06:44:05 PM PDT 24 |
84339752900 ps |
| T56 |
/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1746136633 |
|
|
Aug 17 06:39:33 PM PDT 24 |
Aug 17 06:39:48 PM PDT 24 |
28202000 ps |
| T1080 |
/workspace/coverage/default/54.flash_ctrl_otp_reset.4168764965 |
|
|
Aug 17 06:43:15 PM PDT 24 |
Aug 17 06:45:29 PM PDT 24 |
158170400 ps |
| T1081 |
/workspace/coverage/default/5.flash_ctrl_ro_serr.477249086 |
|
|
Aug 17 06:40:05 PM PDT 24 |
Aug 17 06:42:28 PM PDT 24 |
1245108500 ps |
| T1082 |
/workspace/coverage/default/46.flash_ctrl_alert_test.4185122729 |
|
|
Aug 17 06:43:12 PM PDT 24 |
Aug 17 06:43:25 PM PDT 24 |
59083800 ps |
| T1083 |
/workspace/coverage/default/29.flash_ctrl_prog_reset.1774769635 |
|
|
Aug 17 06:42:12 PM PDT 24 |
Aug 17 06:42:27 PM PDT 24 |
24346900 ps |
| T1084 |
/workspace/coverage/default/41.flash_ctrl_disable.869517521 |
|
|
Aug 17 06:42:56 PM PDT 24 |
Aug 17 06:43:19 PM PDT 24 |
78506300 ps |
| T280 |
/workspace/coverage/default/2.flash_ctrl_wr_intg.1366250502 |
|
|
Aug 17 06:39:45 PM PDT 24 |
Aug 17 06:40:00 PM PDT 24 |
45647800 ps |
| T1085 |
/workspace/coverage/default/25.flash_ctrl_intr_rd.4220938090 |
|
|
Aug 17 06:42:06 PM PDT 24 |
Aug 17 06:44:23 PM PDT 24 |
8368466500 ps |
| T1086 |
/workspace/coverage/default/32.flash_ctrl_smoke.1599793844 |
|
|
Aug 17 06:42:27 PM PDT 24 |
Aug 17 06:45:44 PM PDT 24 |
1678181800 ps |
| T1087 |
/workspace/coverage/default/2.flash_ctrl_stress_all.72539806 |
|
|
Aug 17 06:39:52 PM PDT 24 |
Aug 17 06:52:15 PM PDT 24 |
366341000 ps |
| T1088 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3428501065 |
|
|
Aug 17 06:39:40 PM PDT 24 |
Aug 17 06:40:03 PM PDT 24 |
21636300 ps |
| T1089 |
/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2136837885 |
|
|
Aug 17 06:39:37 PM PDT 24 |
Aug 17 07:29:14 PM PDT 24 |
280762710900 ps |
| T1090 |
/workspace/coverage/default/74.flash_ctrl_otp_reset.23790285 |
|
|
Aug 17 06:43:23 PM PDT 24 |
Aug 17 06:45:37 PM PDT 24 |
318325900 ps |
| T1091 |
/workspace/coverage/default/4.flash_ctrl_ro_derr.2661825668 |
|
|
Aug 17 06:39:48 PM PDT 24 |
Aug 17 06:42:11 PM PDT 24 |
4686885300 ps |
| T1092 |
/workspace/coverage/default/73.flash_ctrl_otp_reset.2669266855 |
|
|
Aug 17 06:43:23 PM PDT 24 |
Aug 17 06:45:36 PM PDT 24 |
37248400 ps |
| T1093 |
/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1970165783 |
|
|
Aug 17 06:41:11 PM PDT 24 |
Aug 17 06:42:02 PM PDT 24 |
10040891100 ps |
| T1094 |
/workspace/coverage/default/16.flash_ctrl_alert_test.93472488 |
|
|
Aug 17 06:41:16 PM PDT 24 |
Aug 17 06:41:29 PM PDT 24 |
69179900 ps |
| T337 |
/workspace/coverage/default/31.flash_ctrl_rw_evict.2371776414 |
|
|
Aug 17 06:42:25 PM PDT 24 |
Aug 17 06:42:58 PM PDT 24 |
43481500 ps |
| T1095 |
/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2812002672 |
|
|
Aug 17 06:40:53 PM PDT 24 |
Aug 17 06:43:11 PM PDT 24 |
5904377400 ps |
| T1096 |
/workspace/coverage/default/43.flash_ctrl_otp_reset.3111517187 |
|
|
Aug 17 06:43:04 PM PDT 24 |
Aug 17 06:44:57 PM PDT 24 |
42376400 ps |
| T1097 |
/workspace/coverage/default/23.flash_ctrl_otp_reset.657178546 |
|
|
Aug 17 06:41:58 PM PDT 24 |
Aug 17 06:44:11 PM PDT 24 |
48758000 ps |
| T1098 |
/workspace/coverage/default/71.flash_ctrl_otp_reset.1710300570 |
|
|
Aug 17 06:43:23 PM PDT 24 |
Aug 17 06:45:38 PM PDT 24 |
154720500 ps |
| T1099 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3582297499 |
|
|
Aug 17 06:42:52 PM PDT 24 |
Aug 17 06:44:25 PM PDT 24 |
3363944000 ps |
| T1100 |
/workspace/coverage/default/4.flash_ctrl_phy_arb.3064293567 |
|
|
Aug 17 06:39:51 PM PDT 24 |
Aug 17 06:47:14 PM PDT 24 |
4027365600 ps |
| T1101 |
/workspace/coverage/default/3.flash_ctrl_otp_reset.4021900305 |
|
|
Aug 17 06:39:56 PM PDT 24 |
Aug 17 06:42:09 PM PDT 24 |
41772400 ps |
| T1102 |
/workspace/coverage/default/43.flash_ctrl_smoke.3486894475 |
|
|
Aug 17 06:43:02 PM PDT 24 |
Aug 17 06:45:53 PM PDT 24 |
288510900 ps |
| T1103 |
/workspace/coverage/default/28.flash_ctrl_sec_info_access.4013081019 |
|
|
Aug 17 06:42:13 PM PDT 24 |
Aug 17 06:43:18 PM PDT 24 |
1786418800 ps |
| T1104 |
/workspace/coverage/default/6.flash_ctrl_rw.894374124 |
|
|
Aug 17 06:40:13 PM PDT 24 |
Aug 17 06:50:12 PM PDT 24 |
54664030600 ps |
| T1105 |
/workspace/coverage/default/33.flash_ctrl_sec_info_access.129744901 |
|
|
Aug 17 06:42:35 PM PDT 24 |
Aug 17 06:43:44 PM PDT 24 |
1172336000 ps |
| T1106 |
/workspace/coverage/default/51.flash_ctrl_connect.689506133 |
|
|
Aug 17 06:43:14 PM PDT 24 |
Aug 17 06:43:30 PM PDT 24 |
22751500 ps |
| T1107 |
/workspace/coverage/default/3.flash_ctrl_serr_address.2058781170 |
|
|
Aug 17 06:39:46 PM PDT 24 |
Aug 17 06:41:13 PM PDT 24 |
1199674200 ps |
| T1108 |
/workspace/coverage/default/60.flash_ctrl_otp_reset.2122338672 |
|
|
Aug 17 06:43:20 PM PDT 24 |
Aug 17 06:45:29 PM PDT 24 |
232013900 ps |
| T1109 |
/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2658917187 |
|
|
Aug 17 06:40:48 PM PDT 24 |
Aug 17 06:54:12 PM PDT 24 |
90144650600 ps |
| T1110 |
/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.818837783 |
|
|
Aug 17 06:40:35 PM PDT 24 |
Aug 17 06:43:27 PM PDT 24 |
6010623000 ps |
| T1111 |
/workspace/coverage/default/43.flash_ctrl_connect.378480688 |
|
|
Aug 17 06:43:00 PM PDT 24 |
Aug 17 06:43:16 PM PDT 24 |
34781900 ps |
| T67 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3391301104 |
|
|
Aug 17 06:38:33 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
44134600 ps |
| T1112 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1490854458 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
41468600 ps |
| T244 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3495390823 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
44742300 ps |
| T101 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2218285274 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
116365500 ps |
| T1113 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3868364172 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
43296500 ps |
| T68 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3796706059 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
598468500 ps |
| T69 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.153325332 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:53:54 PM PDT 24 |
7041987700 ps |
| T202 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.343640717 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
47460300 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3312444170 |
|
|
Aug 17 06:38:16 PM PDT 24 |
Aug 17 06:44:48 PM PDT 24 |
436513600 ps |
| T226 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.237537378 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
86379900 ps |
| T221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.469037196 |
|
|
Aug 17 06:38:14 PM PDT 24 |
Aug 17 06:38:28 PM PDT 24 |
43406700 ps |
| T203 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.969545455 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:53:48 PM PDT 24 |
852307200 ps |
| T227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4273003732 |
|
|
Aug 17 06:38:13 PM PDT 24 |
Aug 17 06:38:28 PM PDT 24 |
35505400 ps |
| T213 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4092584701 |
|
|
Aug 17 06:38:47 PM PDT 24 |
Aug 17 06:39:04 PM PDT 24 |
123588700 ps |
| T245 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1319216501 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
51617500 ps |
| T1114 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3980730109 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:45 PM PDT 24 |
23372300 ps |
| T1115 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3422875427 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
78553100 ps |
| T228 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4197226410 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:39:06 PM PDT 24 |
687551600 ps |
| T214 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3599646819 |
|
|
Aug 17 06:38:26 PM PDT 24 |
Aug 17 06:38:42 PM PDT 24 |
83631800 ps |
| T1116 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1179263470 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
25325100 ps |
| T229 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3849197200 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
65682200 ps |
| T1117 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2951001333 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
24368700 ps |
| T204 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.469903092 |
|
|
Aug 17 06:38:33 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
61544300 ps |
| T215 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4242883466 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
214748900 ps |
| T217 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3752251714 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:53:47 PM PDT 24 |
3835610400 ps |
| T230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.159749633 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:38:52 PM PDT 24 |
378039500 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1837427587 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:38:42 PM PDT 24 |
19480300 ps |
| T216 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3916301139 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
89035900 ps |
| T218 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4119398901 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
61832200 ps |
| T311 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3500297105 |
|
|
Aug 17 06:38:54 PM PDT 24 |
Aug 17 06:39:12 PM PDT 24 |
16892500 ps |
| T350 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1954732323 |
|
|
Aug 17 06:38:49 PM PDT 24 |
Aug 17 06:53:47 PM PDT 24 |
1279884100 ps |
| T1118 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1201929754 |
|
|
Aug 17 06:38:10 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
152719600 ps |
| T231 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1541180290 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:39:01 PM PDT 24 |
116807900 ps |
| T355 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3183736638 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:45:02 PM PDT 24 |
633031900 ps |
| T308 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2412700878 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
17710300 ps |
| T232 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3723472889 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
417895000 ps |
| T309 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1347808785 |
|
|
Aug 17 06:38:53 PM PDT 24 |
Aug 17 06:39:07 PM PDT 24 |
88539200 ps |
| T1119 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2238505005 |
|
|
Aug 17 06:38:44 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
12864300 ps |
| T219 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4228978718 |
|
|
Aug 17 06:38:11 PM PDT 24 |
Aug 17 06:38:30 PM PDT 24 |
113520800 ps |
| T310 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3561477573 |
|
|
Aug 17 06:38:53 PM PDT 24 |
Aug 17 06:39:06 PM PDT 24 |
55518200 ps |
| T1120 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.938982604 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:47 PM PDT 24 |
11973300 ps |
| T1121 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3660092849 |
|
|
Aug 17 06:38:45 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
53199200 ps |
| T1122 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3051118681 |
|
|
Aug 17 06:38:53 PM PDT 24 |
Aug 17 06:39:07 PM PDT 24 |
17535900 ps |
| T233 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2452942788 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
297585400 ps |
| T313 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3119503685 |
|
|
Aug 17 06:38:39 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
21117900 ps |
| T1123 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3947747563 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
101706100 ps |
| T1124 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2879310934 |
|
|
Aug 17 06:38:48 PM PDT 24 |
Aug 17 06:39:06 PM PDT 24 |
611722700 ps |
| T1125 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3212623199 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
20065300 ps |
| T312 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.504062294 |
|
|
Aug 17 06:38:38 PM PDT 24 |
Aug 17 06:38:52 PM PDT 24 |
212480900 ps |
| T1126 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3203987216 |
|
|
Aug 17 06:38:00 PM PDT 24 |
Aug 17 06:38:14 PM PDT 24 |
19518600 ps |
| T1127 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2010635121 |
|
|
Aug 17 06:38:48 PM PDT 24 |
Aug 17 06:39:11 PM PDT 24 |
107204300 ps |
| T314 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3902742653 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
28728800 ps |
| T243 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2700687845 |
|
|
Aug 17 06:38:33 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
215992100 ps |
| T1128 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3306246577 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:39:02 PM PDT 24 |
226768800 ps |
| T1129 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3107409585 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:47 PM PDT 24 |
95964800 ps |
| T1130 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.10565511 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:39:25 PM PDT 24 |
2280647300 ps |
| T1131 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1158658061 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
65488200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2382196815 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
18576500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1947815901 |
|
|
Aug 17 06:38:39 PM PDT 24 |
Aug 17 06:38:52 PM PDT 24 |
20921400 ps |
| T283 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1532792037 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:38:44 PM PDT 24 |
468743200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2116239912 |
|
|
Aug 17 06:38:03 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
77826600 ps |
| T1135 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3827820921 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:55 PM PDT 24 |
82019100 ps |
| T284 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1152110512 |
|
|
Aug 17 06:38:13 PM PDT 24 |
Aug 17 06:38:35 PM PDT 24 |
1090380400 ps |
| T1136 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2743198904 |
|
|
Aug 17 06:38:44 PM PDT 24 |
Aug 17 06:39:01 PM PDT 24 |
44997100 ps |
| T1137 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1753585054 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
58884200 ps |
| T253 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1255589187 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:53:44 PM PDT 24 |
365843700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1208823053 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
652512300 ps |
| T247 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1682394413 |
|
|
Aug 17 06:38:58 PM PDT 24 |
Aug 17 06:39:19 PM PDT 24 |
65854700 ps |
| T222 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2467221934 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:44 PM PDT 24 |
31519400 ps |
| T1139 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.157695190 |
|
|
Aug 17 06:39:03 PM PDT 24 |
Aug 17 06:39:16 PM PDT 24 |
30663200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4203557471 |
|
|
Aug 17 06:38:58 PM PDT 24 |
Aug 17 06:39:11 PM PDT 24 |
29793000 ps |
| T285 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2575343931 |
|
|
Aug 17 06:38:19 PM PDT 24 |
Aug 17 06:38:36 PM PDT 24 |
145083500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.587420351 |
|
|
Aug 17 06:38:46 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
16011100 ps |
| T1142 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3669694503 |
|
|
Aug 17 06:38:34 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
12317700 ps |
| T1143 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.414975981 |
|
|
Aug 17 06:38:13 PM PDT 24 |
Aug 17 06:38:29 PM PDT 24 |
21669200 ps |
| T1144 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3060545567 |
|
|
Aug 17 06:38:58 PM PDT 24 |
Aug 17 06:39:17 PM PDT 24 |
141039800 ps |
| T250 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2698559726 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:39:03 PM PDT 24 |
62806500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3113599341 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
119810000 ps |
| T1146 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1896858159 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
15074300 ps |
| T286 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2853512082 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:39:16 PM PDT 24 |
45012500 ps |
| T223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4164759439 |
|
|
Aug 17 06:38:11 PM PDT 24 |
Aug 17 06:38:24 PM PDT 24 |
35595100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2790802406 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
39849900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.496230959 |
|
|
Aug 17 06:38:28 PM PDT 24 |
Aug 17 06:38:46 PM PDT 24 |
15723900 ps |
| T287 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2506728066 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:39:12 PM PDT 24 |
1827963900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2709029118 |
|
|
Aug 17 06:38:12 PM PDT 24 |
Aug 17 06:39:35 PM PDT 24 |
4750267300 ps |
| T292 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.902404718 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
45688300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1283512337 |
|
|
Aug 17 06:38:49 PM PDT 24 |
Aug 17 06:39:02 PM PDT 24 |
70280200 ps |
| T358 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4036489287 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:53:56 PM PDT 24 |
720153700 ps |
| T1151 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1023321126 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
51982300 ps |
| T351 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1244714498 |
|
|
Aug 17 06:38:11 PM PDT 24 |
Aug 17 06:44:39 PM PDT 24 |
192607400 ps |
| T288 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2581099403 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:39:13 PM PDT 24 |
1665612100 ps |
| T1152 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4062564862 |
|
|
Aug 17 06:38:39 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
49313000 ps |
| T1153 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.228258259 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:38:46 PM PDT 24 |
82248900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2843257481 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:45 PM PDT 24 |
20893200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1920078476 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:47 PM PDT 24 |
158620700 ps |
| T293 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1492095981 |
|
|
Aug 17 06:38:27 PM PDT 24 |
Aug 17 06:38:45 PM PDT 24 |
202275500 ps |
| T1156 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4126194219 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
90203500 ps |
| T1157 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.708662619 |
|
|
Aug 17 06:38:40 PM PDT 24 |
Aug 17 06:39:12 PM PDT 24 |
47241600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3510710919 |
|
|
Aug 17 06:38:34 PM PDT 24 |
Aug 17 06:38:47 PM PDT 24 |
52441800 ps |
| T289 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.85895913 |
|
|
Aug 17 06:38:12 PM PDT 24 |
Aug 17 06:38:30 PM PDT 24 |
112464300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1539477894 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
16673600 ps |
| T1160 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4239852726 |
|
|
Aug 17 06:38:57 PM PDT 24 |
Aug 17 06:39:10 PM PDT 24 |
131024000 ps |
| T1161 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1564910213 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:55 PM PDT 24 |
24725000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4073320549 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
26066200 ps |
| T1163 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.218081240 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
91254600 ps |
| T1164 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3346535577 |
|
|
Aug 17 06:38:34 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
39415400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1680905950 |
|
|
Aug 17 06:38:34 PM PDT 24 |
Aug 17 06:38:52 PM PDT 24 |
149103200 ps |
| T224 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3239915874 |
|
|
Aug 17 06:38:02 PM PDT 24 |
Aug 17 06:38:16 PM PDT 24 |
16087900 ps |
| T352 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.566453426 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:46:23 PM PDT 24 |
1226086800 ps |
| T1166 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2904579677 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
79690300 ps |
| T249 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2563868577 |
|
|
Aug 17 06:38:38 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
306440100 ps |
| T1167 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2259092657 |
|
|
Aug 17 06:38:38 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
70377600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2450381082 |
|
|
Aug 17 06:38:13 PM PDT 24 |
Aug 17 06:38:27 PM PDT 24 |
46552300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2372552512 |
|
|
Aug 17 06:38:26 PM PDT 24 |
Aug 17 06:38:41 PM PDT 24 |
138897200 ps |
| T1170 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2142351518 |
|
|
Aug 17 06:38:45 PM PDT 24 |
Aug 17 06:39:01 PM PDT 24 |
36816200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1758717765 |
|
|
Aug 17 06:38:03 PM PDT 24 |
Aug 17 06:38:17 PM PDT 24 |
29966700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2550161111 |
|
|
Aug 17 06:38:49 PM PDT 24 |
Aug 17 06:39:03 PM PDT 24 |
17831000 ps |
| T290 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1894502935 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
216325200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3421065658 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
41049300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2324087196 |
|
|
Aug 17 06:38:48 PM PDT 24 |
Aug 17 06:39:07 PM PDT 24 |
83498800 ps |
| T291 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4039029767 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
733087800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2732728355 |
|
|
Aug 17 06:38:33 PM PDT 24 |
Aug 17 06:38:46 PM PDT 24 |
96239600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4108162549 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:46 PM PDT 24 |
57884200 ps |
| T1177 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.967609512 |
|
|
Aug 17 06:38:33 PM PDT 24 |
Aug 17 06:38:47 PM PDT 24 |
18951200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3762132130 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
50351100 ps |
| T1179 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1218342127 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
40451500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.479594136 |
|
|
Aug 17 06:38:33 PM PDT 24 |
Aug 17 06:38:46 PM PDT 24 |
51687300 ps |
| T1181 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.647519183 |
|
|
Aug 17 06:38:22 PM PDT 24 |
Aug 17 06:38:40 PM PDT 24 |
112283100 ps |
| T1182 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3568287358 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
81996100 ps |
| T353 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.423255040 |
|
|
Aug 17 06:38:38 PM PDT 24 |
Aug 17 06:46:26 PM PDT 24 |
400771200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2098986642 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
16474400 ps |
| T1184 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2759484748 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
26746500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1794145938 |
|
|
Aug 17 06:38:46 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
15993900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1993022990 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
12144000 ps |
| T357 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2249345519 |
|
|
Aug 17 06:38:34 PM PDT 24 |
Aug 17 06:46:14 PM PDT 24 |
170523500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2920328510 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
153027700 ps |
| T1188 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3461204972 |
|
|
Aug 17 06:38:44 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
18551000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.564077028 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
90376100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2531150921 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:46:20 PM PDT 24 |
440966400 ps |
| T294 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.701725288 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
61218100 ps |
| T1191 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1102765057 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
206044600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.926652778 |
|
|
Aug 17 06:38:13 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
1146777100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.279893748 |
|
|
Aug 17 06:38:10 PM PDT 24 |
Aug 17 06:38:24 PM PDT 24 |
14905200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1803676995 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:44 PM PDT 24 |
17035400 ps |
| T1195 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.718765103 |
|
|
Aug 17 06:38:46 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
17119100 ps |
| T295 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1118125188 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
225698800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.371144724 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
56591300 ps |
| T296 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1664871396 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
178276700 ps |
| T1197 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2501778106 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
30309000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3773849376 |
|
|
Aug 17 06:38:28 PM PDT 24 |
Aug 17 06:38:45 PM PDT 24 |
40120400 ps |
| T1199 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2223901415 |
|
|
Aug 17 06:38:54 PM PDT 24 |
Aug 17 06:39:10 PM PDT 24 |
42633000 ps |
| T1200 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1604605148 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
23588300 ps |
| T354 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3206526344 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:46:10 PM PDT 24 |
882352200 ps |
| T1201 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1345463114 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
35068000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2256940308 |
|
|
Aug 17 06:38:45 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
87830500 ps |
| T1203 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4014562073 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
59418200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1485482944 |
|
|
Aug 17 06:39:01 PM PDT 24 |
Aug 17 06:39:14 PM PDT 24 |
114357100 ps |
| T1205 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2362049141 |
|
|
Aug 17 06:38:17 PM PDT 24 |
Aug 17 06:38:33 PM PDT 24 |
45147200 ps |
| T1206 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.765296308 |
|
|
Aug 17 06:38:20 PM PDT 24 |
Aug 17 06:38:33 PM PDT 24 |
27320600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1339777588 |
|
|
Aug 17 06:38:47 PM PDT 24 |
Aug 17 06:39:08 PM PDT 24 |
14970800 ps |
| T1208 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2154924189 |
|
|
Aug 17 06:38:45 PM PDT 24 |
Aug 17 06:39:05 PM PDT 24 |
61470100 ps |
| T1209 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3478560520 |
|
|
Aug 17 06:38:38 PM PDT 24 |
Aug 17 06:38:55 PM PDT 24 |
19174200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3038464886 |
|
|
Aug 17 06:38:36 PM PDT 24 |
Aug 17 06:38:49 PM PDT 24 |
20058800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1322295377 |
|
|
Aug 17 06:38:34 PM PDT 24 |
Aug 17 06:38:52 PM PDT 24 |
88239500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1521207618 |
|
|
Aug 17 06:38:10 PM PDT 24 |
Aug 17 06:38:30 PM PDT 24 |
385071500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.333463922 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:39:36 PM PDT 24 |
1311743800 ps |
| T356 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1740641051 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:54:04 PM PDT 24 |
1679606400 ps |
| T251 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2501908184 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:53:54 PM PDT 24 |
2996408100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.719020855 |
|
|
Aug 17 06:38:39 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
15261100 ps |
| T1215 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3723610013 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:55 PM PDT 24 |
215963100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4176314738 |
|
|
Aug 17 06:38:56 PM PDT 24 |
Aug 17 06:39:10 PM PDT 24 |
18586100 ps |
| T1217 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2518598022 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:53 PM PDT 24 |
25123200 ps |
| T1218 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3571184858 |
|
|
Aug 17 06:38:47 PM PDT 24 |
Aug 17 06:39:03 PM PDT 24 |
44874000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4137882305 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
121565700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3354868346 |
|
|
Aug 17 06:38:51 PM PDT 24 |
Aug 17 06:39:09 PM PDT 24 |
207593300 ps |
| T1221 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3484327333 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
17129000 ps |
| T225 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1971531469 |
|
|
Aug 17 06:38:30 PM PDT 24 |
Aug 17 06:38:44 PM PDT 24 |
57812600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1620223145 |
|
|
Aug 17 06:38:41 PM PDT 24 |
Aug 17 06:38:54 PM PDT 24 |
21800700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3261165342 |
|
|
Aug 17 06:38:45 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
34723600 ps |
| T349 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2279829947 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:46:12 PM PDT 24 |
334486300 ps |
| T1224 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2906685828 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:52 PM PDT 24 |
152999800 ps |
| T1225 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.768729435 |
|
|
Aug 17 06:38:08 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
2531373000 ps |
| T1226 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2799077865 |
|
|
Aug 17 06:38:47 PM PDT 24 |
Aug 17 06:39:01 PM PDT 24 |
121098500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4025267042 |
|
|
Aug 17 06:38:28 PM PDT 24 |
Aug 17 06:38:44 PM PDT 24 |
261208200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1926610546 |
|
|
Aug 17 06:38:44 PM PDT 24 |
Aug 17 06:38:57 PM PDT 24 |
50355600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2881584758 |
|
|
Aug 17 06:38:39 PM PDT 24 |
Aug 17 06:39:09 PM PDT 24 |
175636700 ps |
| T1230 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2655698432 |
|
|
Aug 17 06:38:38 PM PDT 24 |
Aug 17 06:38:55 PM PDT 24 |
14735400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3400752411 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
125940200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2944667877 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:44 PM PDT 24 |
14663100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2278248317 |
|
|
Aug 17 06:38:11 PM PDT 24 |
Aug 17 06:38:43 PM PDT 24 |
21441100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3882556280 |
|
|
Aug 17 06:38:35 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
26101700 ps |
| T1235 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2373582554 |
|
|
Aug 17 06:38:45 PM PDT 24 |
Aug 17 06:38:59 PM PDT 24 |
16045000 ps |
| T1236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2290009852 |
|
|
Aug 17 06:38:10 PM PDT 24 |
Aug 17 06:38:24 PM PDT 24 |
15166100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1469185971 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
12289100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2758964819 |
|
|
Aug 17 06:38:32 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
164441400 ps |
| T1239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2798088022 |
|
|
Aug 17 06:38:20 PM PDT 24 |
Aug 17 06:39:41 PM PDT 24 |
6400943000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2048951376 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:58 PM PDT 24 |
62535500 ps |
| T1241 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1689653517 |
|
|
Aug 17 06:38:43 PM PDT 24 |
Aug 17 06:39:00 PM PDT 24 |
94427300 ps |
| T248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1666526704 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:46:20 PM PDT 24 |
193273800 ps |
| T1242 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4146811466 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:51 PM PDT 24 |
61495500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2507542964 |
|
|
Aug 17 06:38:12 PM PDT 24 |
Aug 17 06:38:28 PM PDT 24 |
29363400 ps |
| T1244 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2927615874 |
|
|
Aug 17 06:38:42 PM PDT 24 |
Aug 17 06:38:56 PM PDT 24 |
24707300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.404870829 |
|
|
Aug 17 06:38:23 PM PDT 24 |
Aug 17 06:39:03 PM PDT 24 |
509309300 ps |
| T1246 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1077087023 |
|
|
Aug 17 06:38:37 PM PDT 24 |
Aug 17 06:38:50 PM PDT 24 |
21081000 ps |
| T252 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3534481444 |
|
|
Aug 17 06:38:27 PM PDT 24 |
Aug 17 06:53:45 PM PDT 24 |
662571800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3013982107 |
|
|
Aug 17 06:38:31 PM PDT 24 |
Aug 17 06:38:48 PM PDT 24 |
33005700 ps |
| T1248 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2015673148 |
|
|
Aug 17 06:38:29 PM PDT 24 |
Aug 17 06:39:38 PM PDT 24 |
1800398300 ps |
| T1249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.109937605 |
|
|
Aug 17 06:38:11 PM PDT 24 |
Aug 17 06:38:27 PM PDT 24 |
20580600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3069380892 |
|
|
Aug 17 06:38:13 PM PDT 24 |
Aug 17 06:38:29 PM PDT 24 |
61550800 ps |